data_read_40bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

         fifo30_rd_addr_r <= 4'd0;
         fifo31_rd_addr_r <= 4'd0;
         fifo40_rd_addr_r <= 4'd0;
         fifo41_rd_addr_r <= 4'd0;
         fifop_rd_addr_r  <= 4'd0;
      end
      else begin
         fifo00_rd_addr_r <= fifo00_rd_addr;
         fifo01_rd_addr_r <= fifo00_rd_addr;
         fifo10_rd_addr_r <= fifo00_rd_addr;
         fifo11_rd_addr_r <= fifo00_rd_addr;
         fifo20_rd_addr_r <= fifo00_rd_addr;
         fifo21_rd_addr_r <= fifo00_rd_addr;
         fifo30_rd_addr_r <= fifo00_rd_addr;
         fifo31_rd_addr_r <= fifo00_rd_addr;
         fifo40_rd_addr_r <= fifo00_rd_addr;
         fifo41_rd_addr_r <= fifo00_rd_addr;
         fifop_rd_addr_r  <= fifo01_rd_addr; 
      end
   end


   always@(posedge clk90)begin
      if(reset90_r)begin
         first_sdr_data   <= 80'd0;  // ***** honey
         read_valid_data_1_r <= 1'b0;
         read_valid_data_1_r1 <= 1'b0;
         read_valid_data_1_r2 <= 1'b0;
      end
      else begin
         read_valid_data_1_r <= read_valid_data_1;
         read_valid_data_1_r1 <= read_valid_data_1_r;
         read_valid_data_1_r2 <= read_valid_data_1_r1;
         if(read_valid_data_1_r1)begin
            first_sdr_data  <= {fifo_40_data_out_r, fifo_30_data_out_r, 
            fifo_20_data_out_r,  fifo_10_data_out_r,  fifo_00_data_out_r, 
            fifo_41_data_out_r,  fifo_31_data_out_r,  fifo_21_data_out_r,  
	    fifo_11_data_out_r,  fifo_01_data_out_r  };
            
              /*
            
            fifo_00_data_out_r, fifo_01_data_out_r, 
            fifo_10_data_out_r,  fifo_11_data_out_r,  fifo_20_data_out_r, 
            fifo_21_data_out_r,  fifo_30_data_out_r,  fifo_31_data_out_r,  
	    fifo_40_data_out_r,  fifo_41_data_out_r,  	    
	    };*/
         end
      end
   end

   // rd address gray counters
   rd_gray_cntr fifo0_rd_addr_inst (.clk(clk90), .reset(reset90_r), .cnt_en(read_valid_data_1), 
                                    .rgc_gcnt(fifo00_rd_addr));

   rd_gray_cntr fifo1_rd_addr_inst (.clk(clk90), .reset(reset90_r), .cnt_en(read_valid_data_1), 
                                    .rgc_gcnt(fifo01_rd_addr));

         
   // 16X1 fifo instantations


   RAM16X1D fifo0_bit0  (.DPO (fifo_00_data_out[0]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[0]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit0  (.DPO (fifo_01_data_out[0]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[0]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1_n), .WE(fifo_01_wr_en));

   RAM16X1D fifo0_bit1  (.DPO (fifo_00_data_out[1]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[1]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit1  (.DPO (fifo_01_data_out[1]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[1]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0_n), .WE(fifo_01_wr_en));

  RAM16X1D fifo0_bit2  (.DPO (fifo_00_data_out[2]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[2]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit2  (.DPO (fifo_01_data_out[2]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[2]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1_n), .WE(fifo_01_wr_en));

   RAM16X1D fifo0_bit3  (.DPO (fifo_00_data_out[3]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[3]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit3  (.DPO (fifo_01_data_out[3]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[3]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0_n), .WE(fifo_01_wr_en));


   RAM16X1D fifo0_bit4  (.DPO (fifo_00_data_out[4]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[4]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit4  (.DPO (fifo_01_data_out[4]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[4]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1_n), .WE(fifo_01_wr_en));

   RAM16X1D fifo0_bit5  (.DPO (fifo_00_data_out[5]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[5]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit5  (.DPO (fifo_01_data_out[5]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[5]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0_n), .WE(fifo_01_wr_en));

   RAM16X1D fifo0_bit6  (.DPO (fifo_00_data_out[6]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[6]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit6  (.DPO (fifo_01_data_out[6]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[6]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1_n), .WE(fifo_01_wr_en));

   RAM16X1D fifo0_bit7  (.DPO (fifo_00_data_out[7]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[7]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit7  (.DPO (fifo_01_data_out[7]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[7]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0_n), .WE(fifo_01_wr_en));


   RAM16X1D fifo0_bit8  (.DPO (fifo_10_data_out[0]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
                          .A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[8]),
                          .DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]), 
                          .DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs1_delayed_col1), .WE(fifo_10_wr_en));

   RAM16X1D fifo1_bit8  (.DPO (fifo_11_data_out[0]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
                          .A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[8]),
                          .DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]), 
                          .DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs1_delayed_col1_n), .WE(fifo_11_wr_en));

   RAM16X1D fifo0_bit9  (.DPO (fifo_10_data_out[1]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
                          .A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[9]),
                          .DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]), 
                          .DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs1_delayed_col0), .WE(fifo_10_wr_en));

   RAM16X1D fifo1_bit9  (.DPO (fifo_11_data_out[1]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
                          .A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[9]),
                          .DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]), 
                          .DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs1_delayed_col0_n), .WE(fifo_11_wr_en));

  RAM16X1D fifo0_bit10  (.DPO (fifo_10_data_out[2]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
                          .A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[10]),
                          .DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]),