data_read_40bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

`timescale 1ns/100ps
module data_read_40bit (
		 
		 clk90,
                 reset90_r,
                 ddr_dq_in,
                 read_valid_data_1,
                 fifo_00_wr_en,
                 fifo_10_wr_en,
                 fifo_20_wr_en,
                 fifo_30_wr_en,
                 fifo_40_wr_en,
                 fifo_01_wr_en,
                 fifo_11_wr_en,
                 fifo_21_wr_en,
                 fifo_31_wr_en,
                 fifo_41_wr_en,
                 fifo_00_wr_addr,
                 fifo_01_wr_addr,
                 fifo_10_wr_addr,
                 fifo_11_wr_addr,
                 fifo_20_wr_addr,
                 fifo_21_wr_addr,
                 fifo_30_wr_addr,
                 fifo_31_wr_addr,
                 fifo_40_wr_addr,
                 fifo_41_wr_addr,
                 dqs0_delayed_col1,
                 dqs1_delayed_col1,
                 dqs2_delayed_col1,
                 dqs3_delayed_col1,
                 dqs4_delayed_col1,
                 
                 dqs0_delayed_col0,
                 dqs1_delayed_col0,
                 dqs2_delayed_col0,
                 dqs3_delayed_col0,
                 dqs4_delayed_col0,
                 user_output_data,
                 fifo0_rd_addr_val,
                 fifo1_rd_addr_val); 

   
   input     clk90;
   input     reset90_r;
   input     [39:0] ddr_dq_in;   
   input     read_valid_data_1;    
   input     fifo_00_wr_en;
   input     fifo_10_wr_en;
   input     fifo_20_wr_en;
   input     fifo_30_wr_en;
   input     fifo_40_wr_en;
   input     fifo_01_wr_en;
   input     fifo_11_wr_en;
   input     fifo_21_wr_en;
   input     fifo_31_wr_en;
   input     fifo_41_wr_en;
   input     [3:0] fifo_00_wr_addr;
   input     [3:0] fifo_01_wr_addr;
   input     [3:0] fifo_10_wr_addr;
   input     [3:0] fifo_11_wr_addr;
   input     [3:0] fifo_20_wr_addr;
   input     [3:0] fifo_21_wr_addr;
   input     [3:0] fifo_30_wr_addr;
   input     [3:0] fifo_31_wr_addr;
   input     [3:0] fifo_40_wr_addr;
   input     [3:0] fifo_41_wr_addr;
   input     dqs0_delayed_col1;
   input     dqs1_delayed_col1;
   input     dqs2_delayed_col1;
   input     dqs3_delayed_col1;
   input     dqs4_delayed_col1;
   input     dqs0_delayed_col0;
   input     dqs1_delayed_col0;
   input     dqs2_delayed_col0;
   input     dqs3_delayed_col0;
   input     dqs4_delayed_col0;
     
  
   output     [79:0] user_output_data;
   output     [3:0] fifo0_rd_addr_val;
   output     [3:0] fifo1_rd_addr_val;     


   reg read_valid_data_1_r;
   reg read_valid_data_1_r1;
   reg read_valid_data_1_r2;
   reg [3:0] fifo00_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifo01_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifo10_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifo11_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifo20_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifo21_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifo30_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifo31_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifo40_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifo41_rd_addr_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [3:0] fifop_rd_addr_r ;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_00_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_01_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_10_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_11_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_20_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_21_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_30_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_31_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_40_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
   reg [7:0] fifo_41_data_out_r;/* synthesis syn_preserve=1 */ /* synthesis syn_noprune=1 */
  
   reg [79:0] first_sdr_data;

   wire [3:0] fifo00_rd_addr;
   wire [3:0] fifo01_rd_addr;
   wire [7:0] fifo_00_data_out;
   wire [7:0] fifo_01_data_out;
   wire [7:0] fifo_10_data_out;
   wire [7:0] fifo_11_data_out;
   wire [7:0] fifo_20_data_out;
   wire [7:0] fifo_21_data_out;
   wire [7:0] fifo_30_data_out;
   wire [7:0] fifo_31_data_out;
   wire [7:0] fifo_40_data_out;
   wire [7:0] fifo_41_data_out;
   wire dqs0_delayed_col0_n;
   wire dqs1_delayed_col0_n;
   wire dqs2_delayed_col0_n;
   wire dqs3_delayed_col0_n;
   wire dqs4_delayed_col0_n;
   wire dqs0_delayed_col1_n;
   wire dqs1_delayed_col1_n;
   wire dqs2_delayed_col1_n;
   wire dqs3_delayed_col1_n;
   wire dqs4_delayed_col1_n;
  
   assign dqs0_delayed_col0_n = ~ dqs0_delayed_col0;
   assign dqs1_delayed_col0_n = ~ dqs1_delayed_col0;
   assign dqs2_delayed_col0_n = ~ dqs2_delayed_col0;
   assign dqs3_delayed_col0_n = ~ dqs3_delayed_col0;
   assign dqs4_delayed_col0_n = ~ dqs4_delayed_col0;
   assign dqs0_delayed_col1_n = ~ dqs0_delayed_col1;
   assign dqs1_delayed_col1_n = ~ dqs1_delayed_col1;
   assign dqs2_delayed_col1_n = ~ dqs2_delayed_col1;
   assign dqs3_delayed_col1_n = ~ dqs3_delayed_col1;
   assign dqs4_delayed_col1_n = ~ dqs4_delayed_col1;
   assign user_output_data    = first_sdr_data;
   assign fifo0_rd_addr_val   = fifo01_rd_addr;
   assign fifo1_rd_addr_val   = fifo00_rd_addr;


   
   always@(posedge clk90)begin
      if(reset90_r)begin
         fifo_00_data_out_r <= 8'd0;
         fifo_01_data_out_r <= 8'd0;
         fifo_10_data_out_r <= 8'd0;  // *** honey
         fifo_11_data_out_r <= 8'd0;  // *** honey
         fifo_20_data_out_r <= 8'd0;
         fifo_21_data_out_r <= 8'd0;
         fifo_30_data_out_r <= 8'd0;
         fifo_31_data_out_r <= 8'd0;
         fifo_40_data_out_r <= 8'd0;
         fifo_41_data_out_r <= 8'd0;
       end
      else 
      begin
         fifo_00_data_out_r <= fifo_00_data_out;
         fifo_01_data_out_r <= fifo_01_data_out;
         fifo_10_data_out_r <= fifo_10_data_out;
         fifo_11_data_out_r <= fifo_11_data_out;
         fifo_20_data_out_r <= fifo_20_data_out;
         fifo_21_data_out_r <= fifo_21_data_out;
         fifo_30_data_out_r <= fifo_30_data_out;
         fifo_31_data_out_r <= fifo_31_data_out;
         fifo_40_data_out_r <= fifo_40_data_out;
         fifo_41_data_out_r <= fifo_41_data_out;
       end
   end

   always@(posedge clk90)begin
      if(reset90_r)begin
         fifo00_rd_addr_r <= 4'd0;       // *** honey
         fifo01_rd_addr_r <= 4'd0;
         fifo10_rd_addr_r <= 4'd0;
         fifo11_rd_addr_r <= 4'd0;
         fifo20_rd_addr_r <= 4'd0;
         fifo21_rd_addr_r <= 4'd0;