📄 data_path_40bit.v
字号:
.fifo_80_wr_addr (fifo_80_wr_addr),
.fifo_90_wr_addr (fifo_90_wr_addr),
.fifo_01_wr_addr (fifo_01_wr_addr),
.fifo_11_wr_addr (fifo_11_wr_addr),
.fifo_21_wr_addr (fifo_21_wr_addr),
.fifo_31_wr_addr (fifo_31_wr_addr),
.fifo_41_wr_addr (fifo_41_wr_addr),
.fifo_51_wr_addr (fifo_51_wr_addr),
.fifo_61_wr_addr (fifo_61_wr_addr),
.fifo_71_wr_addr (fifo_71_wr_addr),
.fifo_81_wr_addr (fifo_81_wr_addr),
.fifo_91_wr_addr (fifo_91_wr_addr),
.dqs0_delayed_col0 (dqs0_delayed_col0),
.dqs1_delayed_col0 (dqs1_delayed_col0),
.dqs2_delayed_col0 (dqs2_delayed_col0),
.dqs3_delayed_col0 (dqs3_delayed_col0),
.dqs4_delayed_col0 (dqs4_delayed_col0),
.dqs5_delayed_col0 (dqs5_delayed_col0),
.dqs6_delayed_col0 (dqs6_delayed_col0),
.dqs7_delayed_col0 (dqs7_delayed_col0),
.dqs8_delayed_col0 (dqs8_delayed_col0),
.dqs9_delayed_col0 (dqs9_delayed_col0),
.dqs0_delayed_col0_n (dqs0_delayed_col0_n),
.dqs1_delayed_col0_n (dqs1_delayed_col0_n),
.dqs2_delayed_col0_n (dqs2_delayed_col0_n),
.dqs3_delayed_col0_n (dqs3_delayed_col0_n),
.dqs4_delayed_col0_n (dqs4_delayed_col0_n),
.dqs5_delayed_col0_n (dqs5_delayed_col0_n),
.dqs6_delayed_col0_n (dqs6_delayed_col0_n),
.dqs7_delayed_col0_n (dqs7_delayed_col0_n),
.dqs8_delayed_col0_n (dqs8_delayed_col0_n),
.dqs9_delayed_col0_n (dqs9_delayed_col0_n),
.user_output_data (user_output_data),
.fifo_00_rd_addr (fifo_00_rd_addr),
.fifo_01_rd_addr (fifo_01_rd_addr),
.fifo_10_rd_addr (fifo_10_rd_addr),
.fifo_11_rd_addr (fifo_11_rd_addr),
.fifo_20_rd_addr (fifo_20_rd_addr),
.fifo_21_rd_addr (fifo_21_rd_addr),
.fifo_30_rd_addr (fifo_30_rd_addr),
.fifo_31_rd_addr (fifo_31_rd_addr),
.fifo_40_rd_addr (fifo_40_rd_addr),
.fifo_41_rd_addr (fifo_41_rd_addr),
.fifo_50_rd_addr (fifo_50_rd_addr),
.fifo_51_rd_addr (fifo_51_rd_addr),
.fifo_60_rd_addr (fifo_60_rd_addr),
.fifo_61_rd_addr (fifo_61_rd_addr),
.fifo_70_rd_addr (fifo_70_rd_addr),
.fifo_71_rd_addr (fifo_71_rd_addr),
.fifo_80_rd_addr (fifo_80_rd_addr),
.fifo_81_rd_addr (fifo_81_rd_addr),
.fifo_90_rd_addr (fifo_90_rd_addr),
.fifo_91_rd_addr (fifo_91_rd_addr)
);
data_read_controller_40bit data_read_controller0 (
.clk (clk),
.clk90 (clk90),
.reset_r (reset_r),
.reset90_r (reset90_r),
.reset180_r (reset180_r),
.reset270_r (reset270_r),
.rst_dqs_div_in (rst_dqs_div_in),
.delay_sel (delay_sel),
.dqs_int_delay_in0 (dqs_int_delay_in0),
.dqs_int_delay_in1 (dqs_int_delay_in1),
.dqs_int_delay_in2 (dqs_int_delay_in2),
.dqs_int_delay_in3 (dqs_int_delay_in3),
.dqs_int_delay_in4 (dqs_int_delay_in4),
.dqs_int_delay_in5 (dqs_int_delay_in5),
.dqs_int_delay_in6 (dqs_int_delay_in6),
.dqs_int_delay_in7 (dqs_int_delay_in7),
.dqs_int_delay_in8 (dqs_int_delay_in8),
.dqs_int_delay_in9 (dqs_int_delay_in9),
.fifo_00_rd_addr_val (fifo_00_rd_addr),
.fifo_01_rd_addr_val (fifo_01_rd_addr),
.fifo_10_rd_addr_val (fifo_10_rd_addr),
.fifo_11_rd_addr_val (fifo_11_rd_addr),
.fifo_20_rd_addr_val (fifo_20_rd_addr),
.fifo_21_rd_addr_val (fifo_21_rd_addr),
.fifo_30_rd_addr_val (fifo_30_rd_addr),
.fifo_31_rd_addr_val (fifo_31_rd_addr),
.fifo_40_rd_addr_val (fifo_40_rd_addr),
.fifo_41_rd_addr_val (fifo_41_rd_addr),
.fifo_50_rd_addr_val (fifo_50_rd_addr),
.fifo_51_rd_addr_val (fifo_51_rd_addr),
.fifo_60_rd_addr_val (fifo_60_rd_addr),
.fifo_61_rd_addr_val (fifo_61_rd_addr),
.fifo_70_rd_addr_val (fifo_70_rd_addr),
.fifo_71_rd_addr_val (fifo_71_rd_addr),
.fifo_80_rd_addr_val (fifo_80_rd_addr),
.fifo_81_rd_addr_val (fifo_81_rd_addr),
.fifo_90_rd_addr_val (fifo_90_rd_addr),
.fifo_91_rd_addr_val (fifo_91_rd_addr),
.u_data_val (u_data_val),
.read_valid_data_1_val (read_valid_data_1),
.fifo_00_wr_en_val (fifo_00_wr_en),
.fifo_10_wr_en_val (fifo_10_wr_en),
.fifo_20_wr_en_val (fifo_20_wr_en),
.fifo_30_wr_en_val (fifo_30_wr_en),
.fifo_40_wr_en_val (fifo_40_wr_en),
.fifo_50_wr_en_val (fifo_50_wr_en),
.fifo_60_wr_en_val (fifo_60_wr_en),
.fifo_70_wr_en_val (fifo_70_wr_en),
.fifo_80_wr_en_val (fifo_80_wr_en),
.fifo_90_wr_en_val (fifo_90_wr_en),
.fifo_01_wr_en_val (fifo_01_wr_en),
.fifo_11_wr_en_val (fifo_11_wr_en),
.fifo_21_wr_en_val (fifo_21_wr_en),
.fifo_31_wr_en_val (fifo_31_wr_en),
.fifo_41_wr_en_val (fifo_41_wr_en),
.fifo_51_wr_en_val (fifo_51_wr_en),
.fifo_61_wr_en_val (fifo_61_wr_en),
.fifo_71_wr_en_val (fifo_71_wr_en),
.fifo_81_wr_en_val (fifo_81_wr_en),
.fifo_91_wr_en_val (fifo_91_wr_en),
.fifo_00_wr_addr_val (fifo_00_wr_addr),
.fifo_10_wr_addr_val (fifo_10_wr_addr),
.fifo_20_wr_addr_val (fifo_20_wr_addr),
.fifo_30_wr_addr_val (fifo_30_wr_addr),
.fifo_40_wr_addr_val (fifo_40_wr_addr),
.fifo_50_wr_addr_val (fifo_50_wr_addr),
.fifo_60_wr_addr_val (fifo_60_wr_addr),
.fifo_01_wr_addr_val (fifo_01_wr_addr),
.fifo_11_wr_addr_val (fifo_11_wr_addr),
.fifo_21_wr_addr_val (fifo_21_wr_addr),
.fifo_31_wr_addr_val (fifo_31_wr_addr),
.fifo_41_wr_addr_val (fifo_41_wr_addr),
.fifo_51_wr_addr_val (fifo_51_wr_addr),
.fifo_61_wr_addr_val (fifo_61_wr_addr),
.fifo_70_wr_addr_val (fifo_70_wr_addr),
.fifo_71_wr_addr_val (fifo_71_wr_addr),
.fifo_80_wr_addr_val (fifo_80_wr_addr),
.fifo_81_wr_addr_val (fifo_81_wr_addr),
.fifo_90_wr_addr_val (fifo_90_wr_addr),
.fifo_91_wr_addr_val (fifo_91_wr_addr),
.dqs0_delayed_col0_val ( dqs0_delayed_col0),
.dqs1_delayed_col0_val ( dqs1_delayed_col0),
.dqs2_delayed_col0_val ( dqs2_delayed_col0),
.dqs3_delayed_col0_val ( dqs3_delayed_col0),
.dqs4_delayed_col0_val ( dqs4_delayed_col0),
.dqs5_delayed_col0_val ( dqs5_delayed_col0),
.dqs6_delayed_col0_val ( dqs6_delayed_col0),
.dqs7_delayed_col0_val ( dqs7_delayed_col0),
.dqs8_delayed_col0_val ( dqs8_delayed_col0),
.dqs9_delayed_col0_val ( dqs9_delayed_col0),
.dqs0_delayed_col0_n_val ( dqs0_delayed_col0_n),
.dqs1_delayed_col0_n_val ( dqs1_delayed_col0_n),
.dqs2_delayed_col0_n_val ( dqs2_delayed_col0_n),
.dqs3_delayed_col0_n_val ( dqs3_delayed_col0_n),
.dqs4_delayed_col0_n_val ( dqs4_delayed_col0_n),
.dqs5_delayed_col0_n_val ( dqs5_delayed_col0_n),
.dqs6_delayed_col0_n_val ( dqs6_delayed_col0_n),
.dqs7_delayed_col0_n_val ( dqs7_delayed_col0_n),
.dqs8_delayed_col0_n_val ( dqs8_delayed_col0_n),
.dqs9_delayed_col0_n_val ( dqs9_delayed_col0_n)
);
data_write_40bit data_write0 (
.user_input_data (user_input_data),
.user_data_mask ( user_data_mask ),
.clk90 (clk90),
.reset90_r (reset90_r),
.reset270_r (reset270_r),
.write_enable (write_enable),
.write_en_val (write_en_val),
.write_data_falling (write_data_falling),
.write_data_rising (write_data_rising),
.data_mask_f (data_mask_f),
.data_mask_r (data_mask_r)
);
data_path_rst data_path_rst0 (
.clk (clk),
.clk90 (clk90),
//XST_REMOVECOMMENT .clk180 (clk180),
//XST_REMOVECOMMENT .clk270 (clk270),
.reset (reset),
.reset90 (reset90),
.reset180 (reset180),
.reset270 (reset270),
.reset_r (reset_r),
.reset90_r (reset90_r),
.reset180_r (reset180_r),
.reset270_r (reset270_r)
);
endmodule⌨️ 快捷键说明
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