📄 data_read_controller_32bit.v
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dqs_delay dqs_delay2_col0 (
.clk_in(dqs_int_delay_in2),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[2])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay2_col1 (
.clk_in(dqs_int_delay_in2),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[2])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay3_col0 (
.clk_in(dqs_int_delay_in3),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[3])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay3_col1 (
.clk_in(dqs_int_delay_in3),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[3])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay4_col0 (
.clk_in(dqs_int_delay_in4),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[4])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay4_col1 (
.clk_in(dqs_int_delay_in4),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[4])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay5_col0 (
.clk_in(dqs_int_delay_in5),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[5])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay5_col1 (
.clk_in(dqs_int_delay_in5),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[5])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay6_col0 (
.clk_in(dqs_int_delay_in6),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[6])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay6_col1 (
.clk_in(dqs_int_delay_in6),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[6])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay7_col0 (
.clk_in(dqs_int_delay_in7),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[7])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay7_col1 (
.clk_in(dqs_int_delay_in7),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[7])
);
// FIFO Write enable signal generation
fifo_0_wr_en fifo_00_wr_en_inst (
.clk (dqs0_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.dout (fifo_00_wr_en)
);
fifo_1_wr_en fifo_01_wr_en_inst (
.clk (dqs0_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_01_wr_en)
);
fifo_0_wr_en fifo_10_wr_en_inst (
.clk (dqs1_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.dout (fifo_10_wr_en)
);
fifo_1_wr_en fifo_11_wr_en_inst (
.clk (dqs1_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_11_wr_en)
);
fifo_0_wr_en fifo_20_wr_en_inst (
.clk (dqs2_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_2_n),
.dout (fifo_20_wr_en)
);
fifo_1_wr_en fifo_21_wr_en_inst (
.clk (dqs2_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_2_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_21_wr_en)
);
fifo_0_wr_en fifo_30_wr_en_inst (
.clk (dqs3_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_3_n),
.dout (fifo_30_wr_en)
);
fifo_1_wr_en fifo_31_wr_en_inst (
.clk (dqs3_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_3_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_31_wr_en)
);
fifo_0_wr_en fifo_40_wr_en_inst (
.clk (dqs4_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_4_n),
.dout (fifo_40_wr_en)
);
fifo_1_wr_en fifo_41_wr_en_inst (
.clk (dqs4_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_4_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_41_wr_en)
);
fifo_0_wr_en fifo_50_wr_en_inst (
.clk (dqs5_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_5_n),
.dout (fifo_50_wr_en)
);
fifo_1_wr_en fifo_51_wr_en_inst (
.clk (dqs5_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_5_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_51_wr_en)
);
fifo_0_wr_en fifo_60_wr_en_inst (
.clk (dqs6_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_6_n),
.dout (fifo_60_wr_en)
);
fifo_1_wr_en fifo_61_wr_en_inst (
.clk (dqs6_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_6_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_61_wr_en)
);
fifo_0_wr_en fifo_70_wr_en_inst (
.clk (dqs7_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_7_n),
.dout (fifo_70_wr_en)
);
fifo_1_wr_en fifo_71_wr_en_inst (
.clk (dqs7_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_7_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_71_wr_en)
);
//-------------------------------------------------------------------------------------------------
// write pointer gray counter instances
wr_gray_cntr fifo_00_wr_addr_inst (
.clk (dqs0_delayed_col1),
.reset (reset_r),
.cnt_en (fifo_00_wr_en),
.wgc_gcnt (fifo_00_wr_addr)
);
wr_gray_cntr fifo_01_wr_addr_inst (
.clk (dqs0_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_01_wr_en),
.wgc_gcnt (fifo_01_wr_addr)
);
wr_gray_cntr fifo_10_wr_addr_inst (
.clk (dqs1_delayed_col1),
.reset (reset_r),
.cnt_en (fifo_10_wr_en),
.wgc_gcnt (fifo_10_wr_addr)
);
wr_gray_cntr fifo_11_wr_addr_inst (
.clk (dqs1_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_11_wr_en),
.wgc_gcnt (fifo_11_wr_addr)
);
wr_gray_cntr fifo_20_wr_addr_inst (
.clk (dqs2_delayed_col1),
.reset (reset_r),
.cnt_en (fifo_20_wr_en),
.wgc_gcnt (fifo_20_wr_addr)
);
wr_gray_cntr fifo_21_wr_addr_inst (
.clk (dqs2_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_21_wr_en),
.wgc_gcnt (fifo_21_wr_addr)
);
wr_gray_cntr fifo_30_wr_addr_inst (
.clk (dqs3_delayed_col1),
.reset (reset_r),
.cnt_en (fifo_30_wr_en),
.wgc_gcnt (fifo_30_wr_addr)
);
wr_gray_cntr fifo_31_wr_addr_inst (
.clk (dqs3_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_31_wr_en),
.wgc_gcnt (fifo_31_wr_addr)
);
wr_gray_cntr fifo_40_wr_addr_inst (
.clk (dqs4_delayed_col1),
.reset (reset_r),
.cnt_en (fifo_40_wr_en),
.wgc_gcnt (fifo_40_wr_addr)
);
wr_gray_cntr fifo_41_wr_addr_inst (
.clk (dqs4_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_41_wr_en),
.wgc_gcnt (fifo_41_wr_addr)
);
wr_gray_cntr fifo_50_wr_addr_inst (
.clk (dqs5_delayed_col1),
.reset (reset_r),
.cnt_en (fifo_50_wr_en),
.wgc_gcnt (fifo_50_wr_addr)
);
wr_gray_cntr fifo_51_wr_addr_inst (
.clk (dqs5_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_51_wr_en),
.wgc_gcnt (fifo_51_wr_addr)
);
wr_gray_cntr fifo_60_wr_addr_inst (
.clk (dqs6_delayed_col1),
.reset (reset_r),
.cnt_en (fifo_60_wr_en),
.wgc_gcnt (fifo_60_wr_addr)
);
wr_gray_cntr fifo_61_wr_addr_inst (
.clk (dqs6_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_61_wr_en),
.wgc_gcnt (fifo_61_wr_addr)
);
wr_gray_cntr fifo_70_wr_addr_inst (
.clk (dqs7_delayed_col1),
.reset (reset_r),
.cnt_en (fifo_70_wr_en),
.wgc_gcnt (fifo_70_wr_addr)
);
wr_gray_cntr fifo_71_wr_addr_inst (
.clk (dqs7_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_71_wr_en),
.wgc_gcnt (fifo_71_wr_addr)
);
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