ddr1_top_32bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
`include "parameters_32bit.v" 
module  ddr1_top_32bit (

     SYS_CLK,
     SYS_CLKb,              
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
     rst_dqs_div_in,   					
     rst_dqs_div_out,  					
     reset_in,              
     user_input_data,       
user_data_mask,
     user_output_data,      
     user_data_valid,
     user_rst_dqs_div, 
     user_rst_calib,   
     user_dqs_reset,   
     user_dqs_enable,  
     user_write_enable,
     ddr1_dqs,               
     ddr1_dq,                
     ddr1_dm,                
     sys_rst_val,
     sys_rst90_val,
     sys_rst180_val,
     sys_rst270_val,
     clk_int_val,
     clk90_int_val
     
     );
     
     
input     SYS_CLK;
input     SYS_CLKb;
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
input     rst_dqs_div_in;
output	  rst_dqs_div_out;
input     reset_in;
input     [63:0]user_input_data;
input [7:0]user_data_mask;
output    [63:0]user_output_data;
output    user_data_valid;
input    user_rst_dqs_div; 
input    user_rst_calib;   
input    user_dqs_reset;   
input    user_dqs_enable;  
input    user_write_enable;
inout     [3:0]ddr1_dqs;
inout     [31:0]ddr1_dq;
output    [3:0]ddr1_dm;           
output    sys_rst_val;
output    sys_rst90_val;
output    sys_rst180_val;
output    sys_rst270_val;
output    clk_int_val;
output    clk90_int_val;


wire sys_clk_ibuf;  
    
wire [4:0]delay_sel;
wire sys_rst;       
wire sys_rst90;     
wire sys_rst180;    
wire sys_rst270;    
wire clk_int;       
wire clk90_int;     
wire dqs_div_rst;       
wire dqs_int_delay_in0; 
wire dqs_int_delay_in1; 
wire dqs_int_delay_in2; 
wire dqs_int_delay_in3; 
wire [31:0]dq; 
wire write_en_val; 
wire reset90_r;    
wire [3:0]data_mask_f;  
wire [3:0]data_mask_r;  
wire [31:0]write_data_falling;
wire [31:0]write_data_rising; 
wire clk_int_val2;     
wire clk90_int_val2;  


assign clk_int_val2 = clk_int;
assign clk90_int_val2 = clk90_int;

assign sys_rst_val = sys_rst;
assign sys_rst90_val = sys_rst90;
assign sys_rst180_val = sys_rst180;
assign sys_rst270_val = sys_rst270;
assign clk_int_val = clk_int;
assign clk90_int_val = clk90_int;


data_path_32bit data_path0  (
.user_data_mask (user_data_mask),
                                 .user_input_data    (user_input_data),
                                 .clk                (clk_int_val2),
                                 .clk90              (clk90_int_val2),
//XST_REMOVECOMMENT  .clk180 (clk180),
//XST_REMOVECOMMENT  .clk270 (clk270),
                                 .reset              (sys_rst),
                                 .reset90            (sys_rst90),
                                 .reset180           (sys_rst180),
                                 .reset270           (sys_rst270),
                                 .write_enable       (user_write_enable),
                                 .rst_dqs_div_in        (dqs_div_rst),
                                 .delay_sel          (delay_sel),
                                 .dqs_int_delay_in0  (dqs_int_delay_in0),
                                 .dqs_int_delay_in1  (dqs_int_delay_in1),
                                 .dqs_int_delay_in2  (dqs_int_delay_in2),
                                 .dqs_int_delay_in3  (dqs_int_delay_in3),
                                 .dq                 (dq),      
                                 .u_data_val         (user_data_valid),
                                 .user_output_data   (user_output_data),
                                 .write_en_val       (write_en_val),
                                 .reset90_r_val     (reset90_r),
                                 .data_mask_f        (data_mask_f),
                                 .data_mask_r        (data_mask_r),
                                 .write_data_falling (write_data_falling),
                                 .write_data_rising  (write_data_rising)                     
                                );                           
                          		
							
infrastructure infrastructure0 
                                        (
                                         .reset_in          (reset_in),
                                         .sys_clk_ibuf      (sys_clk_ibuf),
                                         .rst_calib1        (user_rst_calib),
                                         .delay_sel_val1_val(delay_sel),
                                         .sys_rst_val       (sys_rst),
                                         .sys_rst90_val     (sys_rst90),
                                         .sys_rst180_val    (sys_rst180),
                                         .sys_rst270_val    (sys_rst270),
                                         .clk_int_val       (clk_int),
                                         .clk90_int_val     (clk90_int)
                                        );  
 iobs iobs0  
                    (
                     .SYS_CLK           (SYS_CLK),  
                     .SYS_CLKb          (SYS_CLKb),
                     .clk               (clk_int_val2),
                     .clk90             (clk90_int_val2),
//XST_REMOVECOMMENT  .clk180 (clk180),
//XST_REMOVECOMMENT  .clk270 (clk270),
                     .rst_dqs_div_int   (user_rst_dqs_div),
                     .dqs_reset         (user_dqs_reset),
                     .dqs_enable        (user_dqs_enable),
                     .ddr_dqs           (ddr1_dqs),
                     .ddr_dq            (ddr1_dq),
                     .write_data_falling(write_data_falling), 
                     .write_data_rising (write_data_rising),
                     .write_en_val      (write_en_val),
                     .reset90_r        (reset90_r),
                     .data_mask_f       (data_mask_f), 
                     .data_mask_r       (data_mask_r),
                     .sys_clk_ibuf      (sys_clk_ibuf),
                     .rst_dqs_div       (dqs_div_rst),
                  		 .rst_dqs_div_in	   (rst_dqs_div_in),
		     .rst_dqs_div_out	  ( rst_dqs_div_out),
                     .dqs_int_delay_in0 (dqs_int_delay_in0),
                     .dqs_int_delay_in1 (dqs_int_delay_in1),
                     .dqs_int_delay_in2 (dqs_int_delay_in2),
                     .dqs_int_delay_in3 (dqs_int_delay_in3), 
                     .dq                (dq),
                     .ddr_dm            (ddr1_dm)
                    );							

endmodule