📄 data_read_32bit.v
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.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit19
( .DPO(fifo_41_data_out[3]),
.SPO( ),
.A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[19]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
//- Nibble5 instantiation
RAM16X1D fifo0_bit20
( .DPO(fifo_50_data_out[0]),
.SPO( ),
.A0(fifo_50_wr_addr[0]),
.A1(fifo_50_wr_addr[1]),
.A2(fifo_50_wr_addr[2]),
.A3(fifo_50_wr_addr[3]),
.D(ddr_dq_in[20]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK(dqs5_delayed_col0),
.WE(fifo_50_wr_en)
);
RAM16X1D fifo1_bit20
( .DPO(fifo_51_data_out[0]),
.SPO( ),
.A0(fifo_51_wr_addr[0]),
.A1(fifo_51_wr_addr[1]),
.A2(fifo_51_wr_addr[2]),
.A3(fifo_51_wr_addr[3]),
.D(ddr_dq_in[20]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK(dqs5_delayed_col0_n),
.WE(fifo_51_wr_en)
);
RAM16X1D fifo0_bit21
( .DPO(fifo_50_data_out[1]),
.SPO( ),
.A0(fifo_50_wr_addr[0]),
.A1(fifo_50_wr_addr[1]),
.A2(fifo_50_wr_addr[2]),
.A3(fifo_50_wr_addr[3]),
.D(ddr_dq_in[21]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK(dqs5_delayed_col0),
.WE(fifo_50_wr_en)
);
RAM16X1D fifo1_bit21
( .DPO(fifo_51_data_out[1]),
.SPO( ),
.A0(fifo_51_wr_addr[0]),
.A1(fifo_51_wr_addr[1]),
.A2(fifo_51_wr_addr[2]),
.A3(fifo_51_wr_addr[3]),
.D(ddr_dq_in[21]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK(dqs5_delayed_col0_n),
.WE(fifo_51_wr_en)
);
RAM16X1D fifo0_bit22
( .DPO(fifo_50_data_out[2]),
.SPO( ),
.A0(fifo_50_wr_addr[0]),
.A1(fifo_50_wr_addr[1]),
.A2(fifo_50_wr_addr[2]),
.A3(fifo_50_wr_addr[3]),
.D(ddr_dq_in[22]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK(dqs5_delayed_col0),
.WE(fifo_50_wr_en)
);
RAM16X1D fifo1_bit22
( .DPO(fifo_51_data_out[2]),
.SPO( ),
.A0(fifo_51_wr_addr[0]),
.A1(fifo_51_wr_addr[1]),
.A2(fifo_51_wr_addr[2]),
.A3(fifo_51_wr_addr[3]),
.D(ddr_dq_in[22]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK(dqs5_delayed_col0_n),
.WE(fifo_51_wr_en)
);
RAM16X1D fifo0_bit23
( .DPO(fifo_50_data_out[3]),
.SPO( ),
.A0(fifo_50_wr_addr[0]),
.A1(fifo_50_wr_addr[1]),
.A2(fifo_50_wr_addr[2]),
.A3(fifo_50_wr_addr[3]),
.D(ddr_dq_in[23]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK(dqs5_delayed_col0),
.WE(fifo_50_wr_en)
);
RAM16X1D fifo1_bit23
( .DPO(fifo_51_data_out[3]),
.SPO( ),
.A0(fifo_51_wr_addr[0]),
.A1(fifo_51_wr_addr[1]),
.A2(fifo_51_wr_addr[2]),
.A3(fifo_51_wr_addr[3]),
.D(ddr_dq_in[23]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK(dqs5_delayed_col0_n),
.WE(fifo_51_wr_en)
);
//Nibble 6 Fifo Instantiation
RAM16X1D fifo0_bit24
( .DPO(fifo_60_data_out[0]),
.SPO( ),
.A0(fifo_60_wr_addr[0]),
.A1(fifo_60_wr_addr[1]),
.A2(fifo_60_wr_addr[2]),
.A3(fifo_60_wr_addr[3]),
.D(ddr_dq_in[24]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK(dqs6_delayed_col0),
.WE(fifo_60_wr_en)
);
RAM16X1D fifo1_bit24
( .DPO(fifo_61_data_out[0]),
.SPO( ),
.A0(fifo_61_wr_addr[0]),
.A1(fifo_61_wr_addr[1]),
.A2(fifo_61_wr_addr[2]),
.A3(fifo_61_wr_addr[3]),
.D(ddr_dq_in[24]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK(dqs6_delayed_col0_n),
.WE(fifo_61_wr_en)
);
RAM16X1D fifo0_bit25
( .DPO(fifo_60_data_out[1]),
.SPO( ),
.A0(fifo_60_wr_addr[0]),
.A1(fifo_60_wr_addr[1]),
.A2(fifo_60_wr_addr[2]),
.A3(fifo_60_wr_addr[3]),
.D(ddr_dq_in[25]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK(dqs6_delayed_col0),
.WE(fifo_60_wr_en)
);
RAM16X1D fifo1_bit25
( .DPO(fifo_61_data_out[1]),
.SPO( ),
.A0(fifo_61_wr_addr[0]),
.A1(fifo_61_wr_addr[1]),
.A2(fifo_61_wr_addr[2]),
.A3(fifo_61_wr_addr[3]),
.D(ddr_dq_in[25]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK(dqs6_delayed_col0_n),
.WE(fifo_61_wr_en)
);
RAM16X1D fifo0_bit26
( .DPO(fifo_60_data_out[2]),
.SPO( ),
.A0(fifo_60_wr_addr[0]),
.A1(fifo_60_wr_addr[1]),
.A2(fifo_60_wr_addr[2]),
.A3(fifo_60_wr_addr[3]),
.D(ddr_dq_in[26]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK(dqs6_delayed_col0),
.WE(fifo_60_wr_en)
);
RAM16X1D fifo1_bit26
( .DPO(fifo_61_data_out[2]),
.SPO( ),
.A0(fifo_61_wr_addr[0]),
.A1(fifo_61_wr_addr[1]),
.A2(fifo_61_wr_addr[2]),
.A3(fifo_61_wr_addr[3]),
.D(ddr_dq_in[26]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK(dqs6_delayed_col0_n),
.WE(fifo_61_wr_en)
);
RAM16X1D fifo0_bit27
( .DPO(fifo_60_data_out[3]),
.SPO( ),
.A0(fifo_60_wr_addr[0]),
.A1(fifo_60_wr_addr[1]),
.A2(fifo_60_wr_addr[2]),
.A3(fifo_60_wr_addr[3]),
.D(ddr_dq_in[27]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK(dqs6_delayed_col0),
.WE(fifo_60_wr_en)
);
RAM16X1D fifo1_bit27
( .DPO(fifo_61_data_out[3]),
.SPO( ),
.A0(fifo_61_wr_addr[0]),
.A1(fifo_61_wr_addr[1]),
.A2(fifo_61_wr_addr[2]),
.A3(fifo_61_wr_addr[3]),
.D(ddr_dq_in[27]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK(dqs6_delayed_col0_n),
.WE(fifo_61_wr_en)
);
//- Nibble7 instantiation
RAM16X1D fifo0_bit28
( .DPO(fifo_70_data_out[0]),
.SPO( ),
.A0(fifo_70_wr_addr[0]),
.A1(fifo_70_wr_addr[1]),
.A2(fifo_70_wr_addr[2]),
.A3(fifo_70_wr_addr[3]),
.D(ddr_dq_in[28]),
.DPRA0(fifo_70_rd_addr[0]),
.DPRA1(fifo_70_rd_addr[1]),
.DPRA2(fifo_70_rd_addr[2]),
.DPRA3(fifo_70_rd_addr[3]),
.WCLK(dqs7_delayed_col0),
.WE(fifo_70_wr_en)
);
RAM16X1D fifo1_bit28
(.DPO(fifo_71_data_out[0]),
.SPO( ),
.A0(fifo_71_wr_addr[0]),
.A1(fifo_71_wr_addr[1]),
.A2(fifo_71_wr_addr[2]),
.A3(fifo_71_wr_addr[3]),
.D(ddr_dq_in[28]),
.DPRA0(fifo_71_rd_addr[0]),
.DPRA1(fifo_71_rd_addr[1]),
.DPRA2(fifo_71_rd_addr[2]),
.DPRA3(fifo_71_rd_addr[3]),
.WCLK(dqs7_delayed_col0_n),
.WE(fifo_71_wr_en)
);
RAM16X1D fifo0_bit29
(.DPO(fifo_70_data_out[1]),
.SPO( ),
.A0(fifo_70_wr_addr[0]),
.A1(fifo_70_wr_addr[1]),
.A2(fifo_70_wr_addr[2]),
.A3(fifo_70_wr_addr[3]),
.D(ddr_dq_in[29]),
.DPRA0(fifo_70_rd_addr[0]),
.DPRA1(fifo_70_rd_addr[1]),
.DPRA2(fifo_70_rd_addr[2]),
.DPRA3(fifo_70_rd_addr[3]),
.WCLK(dqs7_delayed_col0),
.WE(fifo_70_wr_en)
);
RAM16X1D fifo1_bit29
(.DPO(fifo_71_data_out[1]),
.SPO( ),
.A0(fifo_71_wr_addr[0]),
.A1(fifo_71_wr_addr[1]),
.A2(fifo_71_wr_addr[2]),
.A3(fifo_71_wr_addr[3]),
.D(ddr_dq_in[29]),
.DPRA0(fifo_71_rd_addr[0]),
.DPRA1(fifo_71_rd_addr[1]),
.DPRA2(fifo_71_rd_addr[2]),
.DPRA3(fifo_71_rd_addr[3]),
.WCLK(dqs7_delayed_col0_n),
.WE(fifo_71_wr_en)
);
RAM16X1D fifo0_bit30
(.DPO(fifo_70_data_out[2]),
.SPO( ),
.A0(fifo_70_wr_addr[0]),
.A1(fifo_70_wr_addr[1]),
.A2(fifo_70_wr_addr[2]),
.A3(fifo_70_wr_addr[3]),
.D(ddr_dq_in[30]),
.DPRA0(fifo_70_rd_addr[0]),
.DPRA1(fifo_70_rd_addr[1]),
.DPRA2(fifo_70_rd_addr[2]),
.DPRA3(fifo_70_rd_addr[3]),
.WCLK(dqs7_delayed_col0),
.WE(fifo_70_wr_en)
);
RAM16X1D fifo1_bit30
(.DPO(fifo_71_data_out[2]),
.SPO( ),
.A0(fifo_71_wr_addr[0]),
.A1(fifo_71_wr_addr[1]),
.A2(fifo_71_wr_addr[2]),
.A3(fifo_71_wr_addr[3]),
.D(ddr_dq_in[30]),
.DPRA0(fifo_71_rd_addr[0]),
.DPRA1(fifo_71_rd_addr[1]),
.DPRA2(fifo_71_rd_addr[2]),
.DPRA3(fifo_71_rd_addr[3]),
.WCLK(dqs7_delayed_col0_n),
.WE(fifo_71_wr_en)
);
RAM16X1D fifo0_bit31
(.DPO(fifo_70_data_out[3]),
.SPO( ),
.A0(fifo_70_wr_addr[0]),
.A1(fifo_70_wr_addr[1]),
.A2(fifo_70_wr_addr[2]),
.A3(fifo_70_wr_addr[3]),
.D(ddr_dq_in[31]),
.DPRA0(fifo_70_rd_addr[0]),
.DPRA1(fifo_70_rd_addr[1]),
.DPRA2(fifo_70_rd_addr[2]),
.DPRA3(fifo_70_rd_addr[3]),
.WCLK(dqs7_delayed_col0),
.WE(fifo_70_wr_en)
);
RAM16X1D fifo1_bit31
( .DPO(fifo_71_data_out[3]),
.SPO( ),
.A0(fifo_71_wr_addr[0]),
.A1(fifo_71_wr_addr[1]),
.A2(fifo_71_wr_addr[2]),
.A3(fifo_71_wr_addr[3]),
.D(ddr_dq_in[31]),
.DPRA0(fifo_71_rd_addr[0]),
.DPRA1(fifo_71_rd_addr[1]),
.DPRA2(fifo_71_rd_addr[2]),
.DPRA3(fifo_71_rd_addr[3]),
.WCLK(dqs7_delayed_col0_n),
.WE(fifo_71_wr_en)
);
endmodule
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