data_read_controller_32bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

//*********************************************************************
// DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins

// In the current DATA PATH logic DATA CAPTURE part was modified.
// The below changes were made to reduce the resources in 
// the data capture

// in the current architecture data ( dq ) from ddr memory 
// directly stored into the FIFO's.

// Architectural changes :

// Used only TWO FIFOs ( instead of FOUR FIFOs ) 
// Used Single col ( col0 ) dqs_delayed_col signals
// Used Gray Counters for write and read pointers of the FIFOs 

// fbit stage is removed from ddr1_dqbit module ( in the data capture )
// dq_clk stage was removed 
// dqs_clk_div logic was removed
// ddr1_transfer_done logic was removed 
// data valid signals registering in clk90 domain was removed

// fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
// only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic  
// write enable for the FIFOs derived from rst_dqs_div signal


// Code revised by 	: Narayana Murty.
// Date 			      : Nov 18, 2003. 

//*********************************************************************
  `timescale 1ns/100ps
module    data_read_controller_32bit   ( 

     clk,                
     clk90,              
     reset_r,            
     reset90_r,          
     reset180_r,         
     reset270_r,         
     rst_dqs_div_in,     
     delay_sel,          
     dqs_int_delay_in0,  
     dqs_int_delay_in1,       
     dqs_int_delay_in2,  
     dqs_int_delay_in3,       
     dqs_int_delay_in4,            
     dqs_int_delay_in5,                 
     dqs_int_delay_in6, 
     dqs_int_delay_in7,  
                          
     fifo_00_rd_addr_val,      
     fifo_01_rd_addr_val,      
     fifo_10_rd_addr_val,      
     fifo_11_rd_addr_val,      
     fifo_20_rd_addr_val,      
     fifo_21_rd_addr_val,      
     fifo_30_rd_addr_val,      
     fifo_31_rd_addr_val,      
     fifo_40_rd_addr_val,      
     fifo_41_rd_addr_val,      
     fifo_50_rd_addr_val,      
     fifo_51_rd_addr_val,      
     fifo_60_rd_addr_val,      
     fifo_61_rd_addr_val,      
     fifo_70_rd_addr_val,      
     fifo_71_rd_addr_val,      

     u_data_val,   			
     read_valid_data_1_val, 
     fifo_00_wr_en_val,			  
     fifo_10_wr_en_val,			  
     fifo_20_wr_en_val,			  
     fifo_30_wr_en_val,			  
     fifo_40_wr_en_val,			       
     fifo_50_wr_en_val,			            
     fifo_60_wr_en_val,	
     fifo_70_wr_en_val,			  
     		                 
     fifo_01_wr_en_val,			  
     fifo_11_wr_en_val,			  
     fifo_21_wr_en_val,			  
     fifo_31_wr_en_val,			  
     fifo_41_wr_en_val,			       
     fifo_51_wr_en_val,			            
     fifo_61_wr_en_val,			                 
     fifo_71_wr_en_val,			  

     fifo_00_wr_addr_val,   
     fifo_10_wr_addr_val,   
     fifo_20_wr_addr_val,   
     fifo_30_wr_addr_val,   
     fifo_40_wr_addr_val,        
     fifo_50_wr_addr_val,             
     fifo_60_wr_addr_val,                  
     fifo_01_wr_addr_val,        
     fifo_11_wr_addr_val,   
     fifo_21_wr_addr_val,   
     fifo_31_wr_addr_val,   
     fifo_41_wr_addr_val,        
     fifo_51_wr_addr_val,             
     fifo_61_wr_addr_val,                  
     fifo_70_wr_addr_val,   
     fifo_71_wr_addr_val,   

     dqs0_delayed_col0_val, 
     dqs1_delayed_col0_val, 
     dqs2_delayed_col0_val, 
     dqs3_delayed_col0_val, 
     dqs4_delayed_col0_val,      
     dqs5_delayed_col0_val,           
     dqs6_delayed_col0_val,                
     dqs7_delayed_col0_val, 

     dqs0_delayed_col0_n_val,
     dqs1_delayed_col0_n_val,
     dqs2_delayed_col0_n_val, 
     dqs3_delayed_col0_n_val,
     dqs4_delayed_col0_n_val,       
     dqs5_delayed_col0_n_val,           
     dqs6_delayed_col0_n_val,
     dqs7_delayed_col0_n_val
      );

input     clk;
input     clk90;              
input     reset_r;           
input     reset90_r;        
input     reset180_r;        
input     reset270_r;        
input     rst_dqs_div_in;     
input     [4:0]delay_sel;          
input     dqs_int_delay_in0; 
input     dqs_int_delay_in1; 
input     dqs_int_delay_in2; 
input     dqs_int_delay_in3; 
input     dqs_int_delay_in4; 
input     dqs_int_delay_in5; 
input     dqs_int_delay_in6; 
input     dqs_int_delay_in7;  

output     [3:0]fifo_00_rd_addr_val;      
output     [3:0]fifo_01_rd_addr_val; 
output     [3:0]fifo_10_rd_addr_val;      
output     [3:0]fifo_11_rd_addr_val; 
output     [3:0]fifo_20_rd_addr_val;      
output     [3:0]fifo_21_rd_addr_val; 
output     [3:0]fifo_30_rd_addr_val;      
output     [3:0]fifo_31_rd_addr_val; 
output     [3:0]fifo_40_rd_addr_val;      
output     [3:0]fifo_41_rd_addr_val; 
output     [3:0]fifo_50_rd_addr_val;      
output     [3:0]fifo_51_rd_addr_val; 
output     [3:0]fifo_60_rd_addr_val;      
output     [3:0]fifo_61_rd_addr_val; 
output     [3:0]fifo_70_rd_addr_val;      
output     [3:0]fifo_71_rd_addr_val;     
   
    
output     u_data_val;   			
output     read_valid_data_1_val;  
     
output     fifo_00_wr_en_val;			  
output     fifo_10_wr_en_val;			  
output     fifo_20_wr_en_val;			  
output     fifo_30_wr_en_val;			  
output     fifo_40_wr_en_val;			  
output     fifo_50_wr_en_val;			  
output     fifo_60_wr_en_val;			  
output     fifo_70_wr_en_val;			  

output     fifo_01_wr_en_val;			  
output     fifo_11_wr_en_val;			  
output     fifo_21_wr_en_val;			  
output     fifo_31_wr_en_val;			  
output     fifo_41_wr_en_val;			  
output     fifo_51_wr_en_val;			  
output     fifo_61_wr_en_val;	
output     fifo_71_wr_en_val;			  
	
output     [3:0]fifo_00_wr_addr_val;   
output     [3:0]fifo_10_wr_addr_val;   
output     [3:0]fifo_20_wr_addr_val;   
output     [3:0]fifo_30_wr_addr_val;   
output     [3:0]fifo_40_wr_addr_val;   
output     [3:0]fifo_50_wr_addr_val;   
output     [3:0]fifo_60_wr_addr_val; 
output     [3:0]fifo_70_wr_addr_val;   
  
output     [3:0]fifo_01_wr_addr_val;    
output     [3:0]fifo_11_wr_addr_val;    
output     [3:0]fifo_21_wr_addr_val;    
output     [3:0]fifo_31_wr_addr_val;    
output     [3:0]fifo_41_wr_addr_val;         
output     [3:0]fifo_51_wr_addr_val;         
output     [3:0]fifo_61_wr_addr_val;   
output     [3:0]fifo_71_wr_addr_val;    
      
output     dqs0_delayed_col0_val; 
output     dqs1_delayed_col0_val; 
output     dqs2_delayed_col0_val; 
output     dqs3_delayed_col0_val; 
output     dqs4_delayed_col0_val; 
output     dqs5_delayed_col0_val; 
output     dqs6_delayed_col0_val; 
output     dqs7_delayed_col0_val; 

output     dqs0_delayed_col0_n_val;
output     dqs1_delayed_col0_n_val;
output     dqs2_delayed_col0_n_val;
output     dqs3_delayed_col0_n_val;
output     dqs4_delayed_col0_n_val;
output     dqs5_delayed_col0_n_val;
output     dqs6_delayed_col0_n_val;
output     dqs7_delayed_col0_n_val;

reg        u_data_val;
wire dqs_int_delay_in0;
wire dqs_int_delay_in1;
wire dqs_int_delay_in2;
wire dqs_int_delay_in3;
wire dqs_int_delay_in4;
wire dqs_int_delay_in5;
wire dqs_int_delay_in6;
wire dqs_int_delay_in7;

wire [7:0]dqs_delayed_col0;

wire resetn;

wire fifo_00_empty;
wire fifo_01_empty;

wire [3:0] fifo_00_wr_addr;
wire [3:0] fifo_10_wr_addr;
wire [3:0] fifo_20_wr_addr;
wire [3:0] fifo_30_wr_addr;
wire [3:0] fifo_40_wr_addr;
wire [3:0] fifo_50_wr_addr;
wire [3:0] fifo_60_wr_addr;
wire [3:0] fifo_70_wr_addr;

wire [3:0] fifo_01_wr_addr;
wire [3:0] fifo_11_wr_addr;
wire [3:0] fifo_21_wr_addr;
wire [3:0] fifo_31_wr_addr;
wire [3:0] fifo_41_wr_addr;
wire [3:0] fifo_51_wr_addr;
wire [3:0] fifo_61_wr_addr;
wire [3:0] fifo_71_wr_addr;

wire read_valid_data_0_1;
wire read_valid_data_1; 

wire dqs0_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs1_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs2_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs3_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs4_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs5_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs6_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs7_delayed_col0 /* synthesis syn_keep=1 */;

wire dqs0_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs1_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs2_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs3_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs4_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs5_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs6_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs7_delayed_col0_n /* synthesis syn_keep=1 */;

wire 	   TIE_HIGH;


// FIFO WRITE ENABLE SIGNALS

wire 	fifo_00_wr_en;
wire 	fifo_10_wr_en;
wire 	fifo_20_wr_en;
wire 	fifo_30_wr_en;
wire 	fifo_40_wr_en;
wire 	fifo_50_wr_en;
wire 	fifo_60_wr_en;
wire 	fifo_70_wr_en;

wire 	fifo_01_wr_en;
wire 	fifo_11_wr_en;
wire 	fifo_21_wr_en;
wire 	fifo_31_wr_en;
wire 	fifo_41_wr_en;
wire 	fifo_51_wr_en;
wire 	fifo_61_wr_en;
wire 	fifo_71_wr_en;

//signal rst_dqs_delay_n : std_logic;
wire rst_dqs_delay_0_n;
wire rst_dqs_delay_1_n;