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📄 data_read.v

📁 XILINX memory interface generator. XILINX的外部存储器接口。
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          .DPRA0(fifo_11_rd_addr[0]),
          .DPRA1(fifo_11_rd_addr[1]),
          .DPRA2(fifo_11_rd_addr[2]),
          .DPRA3(fifo_11_rd_addr[3]),
          .WCLK(dqs1_delayed_col0_n),          
          .WE(fifo_11_wr_en)
           );                                 
                 
                 
  RAM16X1D fifo0_bit11               
	 ( .DPO(fifo_10_data_out[3]),          
	 .SPO(open),
          .A0(fifo_10_wr_addr[0]),          
          .A1(fifo_10_wr_addr[1]),
          .A2(fifo_10_wr_addr[2]),
          .A3(fifo_10_wr_addr[3]),
          .D(ddr_dq_in[11]),      
          .DPRA0(fifo_10_rd_addr[0]),
          .DPRA1(fifo_10_rd_addr[1]),
          .DPRA2(fifo_10_rd_addr[2]),
          .DPRA3(fifo_10_rd_addr[3]),
          .WCLK(dqs1_delayed_col1),          
          .WE(fifo_10_wr_en)
           );                       

 RAM16X1D fifo1_bit11               
	 ( .DPO(fifo_11_data_out[3]),          
	 .SPO(open),
          .A0(fifo_11_wr_addr[0]),          
          .A1(fifo_11_wr_addr[1]),
          .A2(fifo_11_wr_addr[2]),
          .A3(fifo_11_wr_addr[3]),
          .D(ddr_dq_in[11]),      
          .DPRA0(fifo_11_rd_addr[0]),
          .DPRA1(fifo_11_rd_addr[1]),
          .DPRA2(fifo_11_rd_addr[2]),
          .DPRA3(fifo_11_rd_addr[3]),
          .WCLK(dqs1_delayed_col0_n),          
          .WE(fifo_11_wr_en)
           ); 
           
  RAM16X1D fifo0_bit12               
	 ( .DPO(fifo_10_data_out[4]),          
	 .SPO(open),
          .A0(fifo_10_wr_addr[0]),          
          .A1(fifo_10_wr_addr[1]),
          .A2(fifo_10_wr_addr[2]),
          .A3(fifo_10_wr_addr[3]),
          .D(ddr_dq_in[12]),      
          .DPRA0(fifo_10_rd_addr[0]),
          .DPRA1(fifo_10_rd_addr[1]),
          .DPRA2(fifo_10_rd_addr[2]),
          .DPRA3(fifo_10_rd_addr[3]),
          .WCLK(dqs1_delayed_col1),          
          .WE(fifo_10_wr_en)
           );                       

 RAM16X1D fifo1_bit12               
	 ( .DPO(fifo_11_data_out[4]),          
	 .SPO(open),
          .A0(fifo_11_wr_addr[0]),          
          .A1(fifo_11_wr_addr[1]),
          .A2(fifo_11_wr_addr[2]),
          .A3(fifo_11_wr_addr[3]),
          .D(ddr_dq_in[12]),      
          .DPRA0(fifo_11_rd_addr[0]),
          .DPRA1(fifo_11_rd_addr[1]),
          .DPRA2(fifo_11_rd_addr[2]),
          .DPRA3(fifo_11_rd_addr[3]),
          .WCLK(dqs1_delayed_col0_n),          
          .WE(fifo_11_wr_en)
           );   
           
  RAM16X1D fifo0_bit13               
	 ( .DPO(fifo_10_data_out[5]),          
	 .SPO(open),
          .A0(fifo_10_wr_addr[0]),          
          .A1(fifo_10_wr_addr[1]),
          .A2(fifo_10_wr_addr[2]),
          .A3(fifo_10_wr_addr[3]),
          .D(ddr_dq_in[13]),      
          .DPRA0(fifo_10_rd_addr[0]),
          .DPRA1(fifo_10_rd_addr[1]),
          .DPRA2(fifo_10_rd_addr[2]),
          .DPRA3(fifo_10_rd_addr[3]),
          .WCLK(dqs1_delayed_col1),          
          .WE(fifo_10_wr_en)
           );                       

 RAM16X1D fifo1_bit13               
	 ( .DPO(fifo_11_data_out[5]),          
	 .SPO(open),
          .A0(fifo_11_wr_addr[0]),          
          .A1(fifo_11_wr_addr[1]),
          .A2(fifo_11_wr_addr[2]),
          .A3(fifo_11_wr_addr[3]),
          .D(ddr_dq_in[13]),      
          .DPRA0(fifo_11_rd_addr[0]),
          .DPRA1(fifo_11_rd_addr[1]),
          .DPRA2(fifo_11_rd_addr[2]),
          .DPRA3(fifo_11_rd_addr[3]),
          .WCLK(dqs1_delayed_col0_n),          
          .WE(fifo_11_wr_en)
           );   
           
  RAM16X1D fifo0_bit14               
	 ( .DPO(fifo_10_data_out[6]),          
	 .SPO(open),
          .A0(fifo_10_wr_addr[0]),          
          .A1(fifo_10_wr_addr[1]),
          .A2(fifo_10_wr_addr[2]),
          .A3(fifo_10_wr_addr[3]),
          .D(ddr_dq_in[14]),      
          .DPRA0(fifo_10_rd_addr[0]),
          .DPRA1(fifo_10_rd_addr[1]),
          .DPRA2(fifo_10_rd_addr[2]),
          .DPRA3(fifo_10_rd_addr[3]),
          .WCLK(dqs1_delayed_col1),          
          .WE(fifo_10_wr_en)
           );                       

 RAM16X1D fifo1_bit14               
	 ( .DPO(fifo_11_data_out[6]),          
	 .SPO(open),
          .A0(fifo_11_wr_addr[0]),          
          .A1(fifo_11_wr_addr[1]),
          .A2(fifo_11_wr_addr[2]),
          .A3(fifo_11_wr_addr[3]),
          .D(ddr_dq_in[14]),      
          .DPRA0(fifo_11_rd_addr[0]),
          .DPRA1(fifo_11_rd_addr[1]),
          .DPRA2(fifo_11_rd_addr[2]),
          .DPRA3(fifo_11_rd_addr[3]),
          .WCLK(dqs1_delayed_col0_n),          
          .WE(fifo_11_wr_en)
           );
             
  RAM16X1D fifo0_bit15               
	 ( .DPO(fifo_10_data_out[7]),          
	 .SPO(open),
          .A0(fifo_10_wr_addr[0]),          
          .A1(fifo_10_wr_addr[1]),
          .A2(fifo_10_wr_addr[2]),
          .A3(fifo_10_wr_addr[3]),
          .D(ddr_dq_in[15]),      
          .DPRA0(fifo_10_rd_addr[0]),
          .DPRA1(fifo_10_rd_addr[1]),
          .DPRA2(fifo_10_rd_addr[2]),
          .DPRA3(fifo_10_rd_addr[3]),
          .WCLK(dqs1_delayed_col1),          
          .WE(fifo_10_wr_en)
           );                       

 RAM16X1D fifo1_bit15              
	 ( .DPO(fifo_11_data_out[7]),          
	 .SPO(open),
          .A0(fifo_11_wr_addr[0]),          
          .A1(fifo_11_wr_addr[1]),
          .A2(fifo_11_wr_addr[2]),
          .A3(fifo_11_wr_addr[3]),
          .D(ddr_dq_in[15]),      
          .DPRA0(fifo_11_rd_addr[0]),
          .DPRA1(fifo_11_rd_addr[1]),
          .DPRA2(fifo_11_rd_addr[2]),
          .DPRA3(fifo_11_rd_addr[3]),
          .WCLK(dqs1_delayed_col0_n),          
          .WE(fifo_11_wr_en)
           );            

// Byte2 Fifo instantiation

  RAM16X1D fifo0_bit16               
	 ( .DPO(fifo_20_data_out[0]),          
	 .SPO(open),
          .A0(fifo_20_wr_addr[0]),          
          .A1(fifo_20_wr_addr[1]),
          .A2(fifo_20_wr_addr[2]),
          .A3(fifo_20_wr_addr[3]),
          .D(ddr_dq_in[16]),      
          .DPRA0(fifo_20_rd_addr[0]),
          .DPRA1(fifo_20_rd_addr[1]),
          .DPRA2(fifo_20_rd_addr[2]),
          .DPRA3(fifo_20_rd_addr[3]),
          .WCLK(dqs2_delayed_col1),          
          .WE(fifo_20_wr_en)
           );                       

 RAM16X1D fifo1_bit16              
	 ( .DPO(fifo_21_data_out[0]),          
	 .SPO(open),
          .A0(fifo_21_wr_addr[0]),          
          .A1(fifo_21_wr_addr[1]),
          .A2(fifo_21_wr_addr[2]),
          .A3(fifo_21_wr_addr[3]),
          .D(ddr_dq_in[16]),      
          .DPRA0(fifo_21_rd_addr[0]),
          .DPRA1(fifo_21_rd_addr[1]),
          .DPRA2(fifo_21_rd_addr[2]),
          .DPRA3(fifo_21_rd_addr[3]),
          .WCLK(dqs2_delayed_col0_n),          
          .WE(fifo_21_wr_en)
           );  
           
  RAM16X1D fifo0_bit17               
	 ( .DPO(fifo_20_data_out[1]),          
	 .SPO(open),
          .A0(fifo_20_wr_addr[0]),          
          .A1(fifo_20_wr_addr[1]),
          .A2(fifo_20_wr_addr[2]),
          .A3(fifo_20_wr_addr[3]),
          .D(ddr_dq_in[17]),      
          .DPRA0(fifo_20_rd_addr[0]),
          .DPRA1(fifo_20_rd_addr[1]),
          .DPRA2(fifo_20_rd_addr[2]),
          .DPRA3(fifo_20_rd_addr[3]),
          .WCLK(dqs2_delayed_col1),          
          .WE(fifo_20_wr_en)
           );                       

 RAM16X1D fifo1_bit17              
	 ( .DPO(fifo_21_data_out[1]),          
	 .SPO(open),
          .A0(fifo_21_wr_addr[0]),          
          .A1(fifo_21_wr_addr[1]),
          .A2(fifo_21_wr_addr[2]),
          .A3(fifo_21_wr_addr[3]),
          .D(ddr_dq_in[17]),      
          .DPRA0(fifo_21_rd_addr[0]),
          .DPRA1(fifo_21_rd_addr[1]),
          .DPRA2(fifo_21_rd_addr[2]),
          .DPRA3(fifo_21_rd_addr[3]),
          .WCLK(dqs2_delayed_col0_n),          
          .WE(fifo_21_wr_en)
           );  
  RAM16X1D fifo0_bit18               
	 ( .DPO(fifo_20_data_out[2]),          
	 .SPO(open),
          .A0(fifo_20_wr_addr[0]),          
          .A1(fifo_20_wr_addr[1]),
          .A2(fifo_20_wr_addr[2]),
          .A3(fifo_20_wr_addr[3]),
          .D(ddr_dq_in[18]),      
          .DPRA0(fifo_20_rd_addr[0]),
          .DPRA1(fifo_20_rd_addr[1]),
          .DPRA2(fifo_20_rd_addr[2]),
          .DPRA3(fifo_20_rd_addr[3]),
          .WCLK(dqs2_delayed_col1),          
          .WE(fifo_20_wr_en)
           );                       

 RAM16X1D fifo1_bit18              
	 ( .DPO(fifo_21_data_out[2]),          
	 .SPO(open),
          .A0(fifo_21_wr_addr[0]),          
          .A1(fifo_21_wr_addr[1]),
          .A2(fifo_21_wr_addr[2]),
          .A3(fifo_21_wr_addr[3]),
          .D(ddr_dq_in[18]),      
          .DPRA0(fifo_21_rd_addr[0]),
          .DPRA1(fifo_21_rd_addr[1]),
          .DPRA2(fifo_21_rd_addr[2]),
          .DPRA3(fifo_21_rd_addr[3]),
          .WCLK(dqs2_delayed_col0_n),          
          .WE(fifo_21_wr_en)
           );  
                     
  RAM16X1D fifo0_bit19               
	 ( .DPO(fifo_20_data_out[3]),          
	 .SPO(open),
          .A0(fifo_20_wr_addr[0]),          
          .A1(fifo_20_wr_addr[1]),
          .A2(fifo_20_wr_addr[2]),
          .A3(fifo_20_wr_addr[3]),
          .D(ddr_dq_in[19]),      
          .DPRA0(fifo_20_rd_addr[0]),
          .DPRA1(fifo_20_rd_addr[1]),
          .DPRA2(fifo_20_rd_addr[2]),
          .DPRA3(fifo_20_rd_addr[3]),
          .WCLK(dqs2_delayed_col1),          
          .WE(fifo_20_wr_en)
           );                       

 RAM16X1D fifo1_bit19              
	 ( .DPO(fifo_21_data_out[3]),          
	 .SPO(open),
          .A0(fifo_21_wr_addr[0]),          
          .A1(fifo_21_wr_addr[1]),
          .A2(fifo_21_wr_addr[2]),
          .A3(fifo_21_wr_addr[3]),
          .D(ddr_dq_in[19]),      
          .DPRA0(fifo_21_rd_addr[0]),
          .DPRA1(fifo_21_rd_addr[1]),
          .DPRA2(fifo_21_rd_addr[2]),
          .DPRA3(fifo_21_rd_addr[3]),
          .WCLK(dqs2_delayed_col0_n),          
          .WE(fifo_21_wr_en)
           );  
         
  RAM16X1D fifo0_bit20               
	 ( .DPO(fifo_20_data_out[4]),          
	 .SPO(open),
          .A0(fifo_20_wr_addr[0]),          
          .A1(fifo_20_wr_addr[1]),
          .A2(fifo_20_wr_addr[2]),
          .A3(fifo_20_wr_addr[3]),
          .D(ddr_dq_in[20]),      
          .DPRA0(fifo_20_rd_addr[0]),
          .DPRA1(fifo_20_rd_addr[1]),
          .DPRA2(fifo_20_rd_addr[2]),
          .DPRA3(fifo_20_rd_addr[3]),
          .WCLK(dqs2_delayed_col1),          
          .WE(fifo_20_wr_en)
           );                       

 RAM16X1D fifo1_bit20              
	 ( .DPO(fifo_21_data_out[4]),          
	 .SPO(open),
          .A0(fifo_21_wr_addr[0]),          
          .A1(fifo_21_wr_addr[1]),
          .A2(fifo_21_wr_addr[2]),
          .A3(fifo_21_wr_addr[3]),
          .D(ddr_dq_in[20]),      
          .DPRA0(fifo_21_rd_addr[0]),
          .DPRA1(fifo_21_rd_addr[1]),
          .DPRA2(fifo_21_rd_addr[2]),
          .DPRA3(fifo_21_rd_addr[3]),
          .WCLK(dqs2_delayed_col0_n),          
          .WE(fifo_21_wr_en)
           );  

  RAM16X1D fifo0_bit21               
	 ( .DPO(fifo_20_data_out[5]),          
	 .SPO(open),
          .A0(fifo_20_wr_addr[0]),          
          .A1(fifo_20_wr_addr[1]),
          .A2(fifo_20_wr_addr[2]),
          .A3(fifo_20_wr_addr[3]),
          .D(ddr_dq_in[21]),      
          .DPRA0(fifo_20_rd_addr[0]),
          .DPRA1(fifo_20_rd_addr[1]),
          .DPRA2(fifo_20_rd_addr[2]),
          .DPRA3(fifo_20_rd_addr[3]),
          .WCLK(dqs2_delayed_col1),          
          .WE(fifo_20_wr_en)
           );                       

 RAM16X1D fifo1_bit21              
	 ( .DPO(fifo_21_data_out[5]),          
	 .SPO(open),
          .A0(fifo_21_wr_addr[0]),          
          .A1(fifo_21_wr_addr[1]),
          .A2(fifo_21_wr_addr[2]),
          .A3(fifo_21_wr_addr[3]),
          .D(ddr_dq_in[21]),      
          .DPRA0(fifo_21_rd_addr[0]),
          .DPRA1(fifo_21_rd_addr[1]),
          .DPRA2(fifo_21_rd_addr[2]),
          .DPRA3(fifo_21_rd_addr[3]),
          .WCLK(dqs2_delayed_col0_n),          
          .WE(fifo_21_wr_en)
           );  
  RAM16X1D fifo0_bit22               
	 ( .DPO(fifo_20_data_out[6]),          
	 .SPO(open),
          .A0(fifo_20_wr_addr[0]),          
          .A1(fifo_20_wr_addr[1]),
          .A2(fifo_20_wr_addr[2]),
          .A3(fifo_20_wr_addr[3]),
          .D(ddr_dq_in[22]),      
          .DPRA0(fifo_20_rd_addr[0]),
          .DPRA1(fifo_20_rd_addr[1]),
          .DPRA2(fifo_20_rd_addr[2]),
          .DPRA3(fifo_20_rd_addr[3]),
          .WCLK(dqs2_delayed_col1),          
          .WE(fifo_20_wr_en)
           );                       

 RAM16X1D fifo1_bit22              
	 ( .DPO(fifo_21_data_out[6]),          
	 .SPO(open),
          .A0(fifo_21_wr_addr[0]),          
          .A1(fifo_21_wr_addr[1]),
          .A2(fifo_21_wr_addr[2]),

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