📄 data_read.v
字号:
fifo_70_data_out,fifo_60_data_out,
fifo_50_data_out,fifo_40_data_out,
fifo_30_data_out,fifo_20_data_out,
fifo_10_data_out,fifo_00_data_out,
fifo_171_data_out,fifo_161_data_out,
fifo_151_data_out,fifo_141_data_out,
fifo_131_data_out,fifo_121_data_out,
fifo_111_data_out,fifo_101_data_out,
fifo_91_data_out,fifo_81_data_out,
fifo_71_data_out,fifo_61_data_out,
fifo_51_data_out,fifo_41_data_out,
fifo_31_data_out,fifo_21_data_out,
fifo_11_data_out,fifo_01_data_out
};
else
first_sdr_data <= first_sdr_data;
end
end
//*************************************************************************************************************************
// Dual Port RAM 16x1 instantiations (fifo0 // Positive edge, fifo1 -- Trailing edge)
//*************************************************************************************************************************
//- Byte0 instantiation
RAM16X1D fifo0_bit0
( .DPO(fifo_00_data_out[0]),
.SPO(open),
.A0(fifo_00_wr_addr[0]),
.A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]),
.A3(fifo_00_wr_addr[3]),
.D(ddr_dq_in[0]),
.DPRA0(fifo_00_rd_addr[0]),
.DPRA1(fifo_00_rd_addr[1]),
.DPRA2(fifo_00_rd_addr[2]),
.DPRA3(fifo_00_rd_addr[3]),
.WCLK(dqs0_delayed_col1),
.WE(fifo_00_wr_en)
);
RAM16X1D fifo1_bit0
( .DPO(fifo_01_data_out[0]),
.SPO(open),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[0]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
RAM16X1D fifo0_bit1
( .DPO(fifo_00_data_out[1]),
.SPO(open),
.A0(fifo_00_wr_addr[0]),
.A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]),
.A3(fifo_00_wr_addr[3]),
.D(ddr_dq_in[1]),
.DPRA0(fifo_00_rd_addr[0]),
.DPRA1(fifo_00_rd_addr[1]),
.DPRA2(fifo_00_rd_addr[2]),
.DPRA3(fifo_00_rd_addr[3]),
.WCLK(dqs0_delayed_col1),
.WE(fifo_00_wr_en)
);
RAM16X1D fifo1_bit1
( .DPO(fifo_01_data_out[1]),
.SPO(open),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[1]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
RAM16X1D fifo0_bit2
( .DPO(fifo_00_data_out[2]),
.SPO(open),
.A0(fifo_00_wr_addr[0]),
.A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]),
.A3(fifo_00_wr_addr[3]),
.D(ddr_dq_in[2]),
.DPRA0(fifo_00_rd_addr[0]),
.DPRA1(fifo_00_rd_addr[1]),
.DPRA2(fifo_00_rd_addr[2]),
.DPRA3(fifo_00_rd_addr[3]),
.WCLK(dqs0_delayed_col1),
.WE(fifo_00_wr_en)
);
RAM16X1D fifo1_bit2
( .DPO(fifo_01_data_out[2]),
.SPO(open),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[2]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
RAM16X1D fifo0_bit3
( .DPO(fifo_00_data_out[3]),
.SPO(open),
.A0(fifo_00_wr_addr[0]),
.A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]),
.A3(fifo_00_wr_addr[3]),
.D(ddr_dq_in[3]),
.DPRA0(fifo_00_rd_addr[0]),
.DPRA1(fifo_00_rd_addr[1]),
.DPRA2(fifo_00_rd_addr[2]),
.DPRA3(fifo_00_rd_addr[3]),
.WCLK(dqs0_delayed_col1),
.WE(fifo_00_wr_en)
);
RAM16X1D fifo1_bit3
( .DPO(fifo_01_data_out[3]),
.SPO(open),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[3]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
RAM16X1D fifo0_bit4
( .DPO(fifo_00_data_out[4]),
.SPO(open),
.A0(fifo_00_wr_addr[0]),
.A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]),
.A3(fifo_00_wr_addr[3]),
.D(ddr_dq_in[4]),
.DPRA0(fifo_00_rd_addr[0]),
.DPRA1(fifo_00_rd_addr[1]),
.DPRA2(fifo_00_rd_addr[2]),
.DPRA3(fifo_00_rd_addr[3]),
.WCLK(dqs0_delayed_col1),
.WE(fifo_00_wr_en)
);
RAM16X1D fifo1_bit4
( .DPO(fifo_01_data_out[4]),
.SPO(open),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[4]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
RAM16X1D fifo0_bit5
( .DPO(fifo_00_data_out[5]),
.SPO(open),
.A0(fifo_00_wr_addr[0]),
.A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]),
.A3(fifo_00_wr_addr[3]),
.D(ddr_dq_in[5]),
.DPRA0(fifo_00_rd_addr[0]),
.DPRA1(fifo_00_rd_addr[1]),
.DPRA2(fifo_00_rd_addr[2]),
.DPRA3(fifo_00_rd_addr[3]),
.WCLK(dqs0_delayed_col1),
.WE(fifo_00_wr_en)
);
RAM16X1D fifo1_bit5
( .DPO(fifo_01_data_out[5]),
.SPO(open),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[5]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
RAM16X1D fifo0_bit6
( .DPO(fifo_00_data_out[6]),
.SPO(open),
.A0(fifo_00_wr_addr[0]),
.A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]),
.A3(fifo_00_wr_addr[3]),
.D(ddr_dq_in[6]),
.DPRA0(fifo_00_rd_addr[0]),
.DPRA1(fifo_00_rd_addr[1]),
.DPRA2(fifo_00_rd_addr[2]),
.DPRA3(fifo_00_rd_addr[3]),
.WCLK(dqs0_delayed_col1),
.WE(fifo_00_wr_en)
);
RAM16X1D fifo1_bit6
( .DPO(fifo_01_data_out[6]),
.SPO(open),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[6]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
RAM16X1D fifo0_bit7
( .DPO(fifo_00_data_out[7]),
.SPO(open),
.A0(fifo_00_wr_addr[0]),
.A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]),
.A3(fifo_00_wr_addr[3]),
.D(ddr_dq_in[7]),
.DPRA0(fifo_00_rd_addr[0]),
.DPRA1(fifo_00_rd_addr[1]),
.DPRA2(fifo_00_rd_addr[2]),
.DPRA3(fifo_00_rd_addr[3]),
.WCLK(dqs0_delayed_col1),
.WE(fifo_00_wr_en)
);
RAM16X1D fifo1_bit7
( .DPO(fifo_01_data_out[7]),
.SPO(open),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[7]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
// Byte1 Fifo instantiation
RAM16X1D fifo0_bit8
( .DPO(fifo_10_data_out[0]),
.SPO(open),
.A0(fifo_10_wr_addr[0]),
.A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]),
.A3(fifo_10_wr_addr[3]),
.D(ddr_dq_in[8]),
.DPRA0(fifo_10_rd_addr[0]),
.DPRA1(fifo_10_rd_addr[1]),
.DPRA2(fifo_10_rd_addr[2]),
.DPRA3(fifo_10_rd_addr[3]),
.WCLK(dqs1_delayed_col1),
.WE(fifo_10_wr_en)
);
RAM16X1D fifo1_bit8
( .DPO(fifo_11_data_out[0]),
.SPO(open),
.A0(fifo_11_wr_addr[0]),
.A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]),
.A3(fifo_11_wr_addr[3]),
.D(ddr_dq_in[8]),
.DPRA0(fifo_11_rd_addr[0]),
.DPRA1(fifo_11_rd_addr[1]),
.DPRA2(fifo_11_rd_addr[2]),
.DPRA3(fifo_11_rd_addr[3]),
.WCLK(dqs1_delayed_col0_n),
.WE(fifo_11_wr_en)
);
RAM16X1D fifo0_bit9
( .DPO(fifo_10_data_out[1]),
.SPO(open),
.A0(fifo_10_wr_addr[0]),
.A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]),
.A3(fifo_10_wr_addr[3]),
.D(ddr_dq_in[9]),
.DPRA0(fifo_10_rd_addr[0]),
.DPRA1(fifo_10_rd_addr[1]),
.DPRA2(fifo_10_rd_addr[2]),
.DPRA3(fifo_10_rd_addr[3]),
.WCLK(dqs1_delayed_col1),
.WE(fifo_10_wr_en)
);
RAM16X1D fifo1_bit9
( .DPO(fifo_11_data_out[1]),
.SPO(open),
.A0(fifo_11_wr_addr[0]),
.A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]),
.A3(fifo_11_wr_addr[3]),
.D(ddr_dq_in[9]),
.DPRA0(fifo_11_rd_addr[0]),
.DPRA1(fifo_11_rd_addr[1]),
.DPRA2(fifo_11_rd_addr[2]),
.DPRA3(fifo_11_rd_addr[3]),
.WCLK(dqs1_delayed_col0_n),
.WE(fifo_11_wr_en)
);
RAM16X1D fifo0_bit10
( .DPO(fifo_10_data_out[2]),
.SPO(open),
.A0(fifo_10_wr_addr[0]),
.A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]),
.A3(fifo_10_wr_addr[3]),
.D(ddr_dq_in[10]),
.DPRA0(fifo_10_rd_addr[0]),
.DPRA1(fifo_10_rd_addr[1]),
.DPRA2(fifo_10_rd_addr[2]),
.DPRA3(fifo_10_rd_addr[3]),
.WCLK(dqs1_delayed_col1),
.WE(fifo_10_wr_en)
);
RAM16X1D fifo1_bit10
( .DPO(fifo_11_data_out[2]),
.SPO(open),
.A0(fifo_11_wr_addr[0]),
.A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]),
.A3(fifo_11_wr_addr[3]),
.D(ddr_dq_in[10]),
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -