data_read.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
module data_read (

     clk,               
     clk90,             
     reset90_r,         
     reset270_r,        
     ddr_dq_in,         
     read_valid_data_1,  
     fifo_00_wr_en,			
     fifo_10_wr_en,			
     fifo_20_wr_en,			
     fifo_30_wr_en,			
     fifo_40_wr_en,			
     fifo_50_wr_en,			
     fifo_60_wr_en,			
     fifo_70_wr_en,			
     fifo_80_wr_en,			
     fifo_90_wr_en,	
     fifo_100_wr_en,			
     fifo_110_wr_en,			
     fifo_120_wr_en,			
     fifo_130_wr_en,			
     fifo_140_wr_en,			
     fifo_150_wr_en,			
     fifo_160_wr_en,			
     fifo_170_wr_en,			
          		
     fifo_01_wr_en,			
     fifo_11_wr_en,			
     fifo_21_wr_en,			
     fifo_31_wr_en,			
     fifo_41_wr_en,			
     fifo_51_wr_en,			
     fifo_61_wr_en,			
     fifo_71_wr_en,			
     fifo_81_wr_en,			
     fifo_91_wr_en,	
     fifo_101_wr_en,			
     fifo_111_wr_en,			
     fifo_121_wr_en,			
     fifo_131_wr_en,			
     fifo_141_wr_en,			
     fifo_151_wr_en,			     		
     fifo_161_wr_en,			
     fifo_171_wr_en,			
     
     fifo_00_wr_addr,    
     fifo_01_wr_addr,    
     fifo_10_wr_addr,    
     fifo_11_wr_addr,    
     fifo_20_wr_addr,    
     fifo_21_wr_addr,    
     fifo_30_wr_addr,    
     fifo_31_wr_addr,    
     fifo_40_wr_addr,    
     fifo_41_wr_addr,    
     fifo_50_wr_addr,    
     fifo_51_wr_addr,    
     fifo_60_wr_addr,    
     fifo_61_wr_addr,    
     fifo_70_wr_addr,    
     fifo_71_wr_addr,    
     fifo_80_wr_addr,    
     fifo_81_wr_addr,    
     fifo_90_wr_addr,    
     fifo_91_wr_addr,
     fifo_100_wr_addr,    
     fifo_101_wr_addr,    
     fifo_110_wr_addr,    
     fifo_111_wr_addr,    
     fifo_120_wr_addr,    
     fifo_121_wr_addr,    
     fifo_130_wr_addr,    
     fifo_131_wr_addr,    
     fifo_140_wr_addr,    
     fifo_141_wr_addr,    
     fifo_150_wr_addr,    
     fifo_151_wr_addr, 
     fifo_160_wr_addr,    
     fifo_161_wr_addr,    
     fifo_170_wr_addr,    
     fifo_171_wr_addr,    
     
                 
     dqs0_delayed_col1,  
     dqs1_delayed_col1,  
     dqs2_delayed_col1,  
     dqs3_delayed_col1,  
     dqs4_delayed_col1,  
     dqs5_delayed_col1,  
     dqs6_delayed_col1,  
     dqs7_delayed_col1,  
     dqs8_delayed_col1,  
     dqs9_delayed_col1,
     dqs10_delayed_col1,  
     dqs11_delayed_col1,  
     dqs12_delayed_col1,  
     dqs13_delayed_col1,  
     dqs14_delayed_col1,  
     dqs15_delayed_col1,   
     dqs16_delayed_col1,  
     dqs17_delayed_col1,  
     
                
     dqs0_delayed_col0_n,
     dqs1_delayed_col0_n,
     dqs2_delayed_col0_n,
     dqs3_delayed_col0_n,
     dqs4_delayed_col0_n,
     dqs5_delayed_col0_n,
     dqs6_delayed_col0_n,
     dqs7_delayed_col0_n,
     dqs8_delayed_col0_n,
     dqs9_delayed_col0_n,
     dqs10_delayed_col0_n,
     dqs11_delayed_col0_n,
     dqs12_delayed_col0_n,
     dqs13_delayed_col0_n,
     dqs14_delayed_col0_n,
     dqs15_delayed_col0_n,          
     dqs16_delayed_col0_n,
     dqs17_delayed_col0_n,
     
     user_output_data,
     fifo_00_rd_addr,
     fifo_01_rd_addr,
     fifo_10_rd_addr,
     fifo_11_rd_addr,
     fifo_20_rd_addr,
     fifo_21_rd_addr,
     fifo_30_rd_addr,
     fifo_31_rd_addr,
     fifo_40_rd_addr,
     fifo_41_rd_addr,
     fifo_50_rd_addr,
     fifo_51_rd_addr,
     fifo_60_rd_addr,
     fifo_61_rd_addr,
     fifo_70_rd_addr,
     fifo_71_rd_addr,
     fifo_80_rd_addr,
     fifo_81_rd_addr,
     fifo_90_rd_addr,
     fifo_91_rd_addr,
     fifo_100_rd_addr,
     fifo_101_rd_addr,
     fifo_110_rd_addr,
     fifo_111_rd_addr,
     fifo_120_rd_addr,
     fifo_121_rd_addr,
     fifo_130_rd_addr,
     fifo_131_rd_addr,
     fifo_140_rd_addr,
     fifo_141_rd_addr,
     fifo_150_rd_addr,
     fifo_151_rd_addr,
     fifo_160_rd_addr,
     fifo_161_rd_addr,
     fifo_170_rd_addr,
     fifo_171_rd_addr
);

 

input     clk;       
input     clk90;     
input     reset90_r; 
input     reset270_r;

input     [143:0]ddr_dq_in;
input     read_valid_data_1;
     
input     fifo_00_wr_en;
input     fifo_10_wr_en;
input     fifo_20_wr_en;			
input     fifo_30_wr_en;			
input     fifo_40_wr_en;			
input     fifo_50_wr_en;			
input     fifo_60_wr_en;			
input     fifo_70_wr_en;			
input     fifo_80_wr_en;			
input     fifo_90_wr_en;
input     fifo_100_wr_en;
input     fifo_110_wr_en;
input     fifo_120_wr_en;			
input     fifo_130_wr_en;			
input     fifo_140_wr_en;			
input     fifo_150_wr_en;		
input     fifo_160_wr_en;			
input     fifo_170_wr_en;			

				
input     fifo_01_wr_en;			
input     fifo_11_wr_en;			
input     fifo_21_wr_en;			
input     fifo_31_wr_en;			
input     fifo_41_wr_en;			
input     fifo_51_wr_en;			
input     fifo_61_wr_en;			
input     fifo_71_wr_en;			
input     fifo_81_wr_en;			
input     fifo_91_wr_en;
input     fifo_101_wr_en;			
input     fifo_111_wr_en;			
input     fifo_121_wr_en;			
input     fifo_131_wr_en;			
input     fifo_141_wr_en;			
input     fifo_151_wr_en;			
input     fifo_161_wr_en;			
input     fifo_171_wr_en;			

					
input     [3:0]fifo_00_wr_addr; 
input     [3:0]fifo_01_wr_addr; 
input     [3:0]fifo_10_wr_addr; 
input     [3:0]fifo_11_wr_addr; 
input     [3:0]fifo_20_wr_addr; 
input     [3:0]fifo_21_wr_addr; 
input     [3:0]fifo_30_wr_addr; 
input     [3:0]fifo_31_wr_addr; 
input     [3:0]fifo_40_wr_addr; 
input     [3:0]fifo_41_wr_addr; 
input     [3:0]fifo_50_wr_addr; 
input     [3:0]fifo_51_wr_addr; 
input     [3:0]fifo_60_wr_addr; 
input     [3:0]fifo_61_wr_addr; 
input     [3:0]fifo_70_wr_addr; 
input     [3:0]fifo_71_wr_addr; 
input     [3:0]fifo_80_wr_addr; 
input     [3:0]fifo_81_wr_addr;    
input     [3:0]fifo_90_wr_addr; 
input     [3:0]fifo_91_wr_addr;  
input     [3:0]fifo_100_wr_addr; 
input     [3:0]fifo_101_wr_addr; 
input     [3:0]fifo_110_wr_addr; 
input     [3:0]fifo_111_wr_addr; 
input     [3:0]fifo_120_wr_addr; 
input     [3:0]fifo_121_wr_addr; 
input     [3:0]fifo_130_wr_addr; 
input     [3:0]fifo_131_wr_addr; 
input     [3:0]fifo_140_wr_addr; 
input     [3:0]fifo_141_wr_addr; 
input     [3:0]fifo_150_wr_addr; 
input     [3:0]fifo_151_wr_addr;   
input     [3:0]fifo_160_wr_addr; 
input     [3:0]fifo_161_wr_addr; 
input     [3:0]fifo_170_wr_addr; 
input     [3:0]fifo_171_wr_addr; 

		
input     dqs0_delayed_col1;  
input     dqs1_delayed_col1;  
input     dqs2_delayed_col1;  
input     dqs3_delayed_col1;  
input     dqs4_delayed_col1;  
input     dqs5_delayed_col1;  
input     dqs6_delayed_col1;  
input     dqs7_delayed_col1;  
input     dqs8_delayed_col1;  
input     dqs9_delayed_col1;
input     dqs10_delayed_col1;  
input     dqs11_delayed_col1;  
input     dqs12_delayed_col1;  
input     dqs13_delayed_col1;  
input     dqs14_delayed_col1;  
input     dqs15_delayed_col1; 
input     dqs16_delayed_col1;  
input     dqs17_delayed_col1;  
        
input     dqs0_delayed_col0_n;
input     dqs1_delayed_col0_n;
input     dqs2_delayed_col0_n;
input     dqs3_delayed_col0_n;
input     dqs4_delayed_col0_n;
input     dqs5_delayed_col0_n;
input     dqs6_delayed_col0_n;
input     dqs7_delayed_col0_n;
input     dqs8_delayed_col0_n;
input     dqs9_delayed_col0_n; 
input     dqs10_delayed_col0_n;
input     dqs11_delayed_col0_n;
input     dqs12_delayed_col0_n;
input     dqs13_delayed_col0_n;
input     dqs14_delayed_col0_n;
input     dqs15_delayed_col0_n;    
input     dqs16_delayed_col0_n;
input     dqs17_delayed_col0_n;

output     [287:0]user_output_data; 

input     [3:0]fifo_00_rd_addr;
input     [3:0]fifo_01_rd_addr;
input     [3:0]fifo_10_rd_addr;
input     [3:0]fifo_11_rd_addr;
input     [3:0]fifo_20_rd_addr;
input     [3:0]fifo_21_rd_addr;
input     [3:0]fifo_30_rd_addr;
input     [3:0]fifo_31_rd_addr;
input     [3:0]fifo_40_rd_addr;
input     [3:0]fifo_41_rd_addr;
input     [3:0]fifo_50_rd_addr;
input     [3:0]fifo_51_rd_addr;
input     [3:0]fifo_60_rd_addr;
input     [3:0]fifo_61_rd_addr;
input     [3:0]fifo_70_rd_addr;
input     [3:0]fifo_71_rd_addr;
input     [3:0]fifo_80_rd_addr;
input     [3:0]fifo_81_rd_addr;
input     [3:0]fifo_90_rd_addr;
input     [3:0]fifo_91_rd_addr;
input     [3:0]fifo_100_rd_addr;
input     [3:0]fifo_101_rd_addr;
input     [3:0]fifo_110_rd_addr;
input     [3:0]fifo_111_rd_addr;
input     [3:0]fifo_120_rd_addr;
input     [3:0]fifo_121_rd_addr;
input     [3:0]fifo_130_rd_addr;
input     [3:0]fifo_131_rd_addr;
input     [3:0]fifo_140_rd_addr;
input     [3:0]fifo_141_rd_addr;
input     [3:0]fifo_150_rd_addr;
input     [3:0]fifo_151_rd_addr;
input     [3:0]fifo_160_rd_addr;
input     [3:0]fifo_161_rd_addr;
input     [3:0]fifo_170_rd_addr;
input     [3:0]fifo_171_rd_addr;

wire [7:0]fifo_00_data_out;
wire [7:0]fifo_01_data_out;
wire [7:0]fifo_10_data_out;
wire [7:0]fifo_11_data_out;
wire [7:0]fifo_20_data_out;
wire [7:0]fifo_21_data_out;
wire [7:0]fifo_30_data_out;
wire [7:0]fifo_31_data_out;
wire [7:0]fifo_40_data_out;
wire [7:0]fifo_41_data_out;
wire [7:0]fifo_50_data_out;
wire [7:0]fifo_51_data_out;
wire [7:0]fifo_60_data_out;
wire [7:0]fifo_61_data_out;
wire [7:0]fifo_70_data_out;
wire [7:0]fifo_71_data_out;
wire [7:0]fifo_80_data_out;
wire [7:0]fifo_81_data_out;
wire [7:0]fifo_90_data_out;
wire [7:0]fifo_91_data_out;
wire [7:0]fifo_100_data_out;
wire [7:0]fifo_101_data_out;
wire [7:0]fifo_110_data_out;
wire [7:0]fifo_111_data_out;
wire [7:0]fifo_120_data_out;
wire [7:0]fifo_121_data_out;
wire [7:0]fifo_130_data_out;
wire [7:0]fifo_131_data_out;
wire [7:0]fifo_140_data_out;
wire [7:0]fifo_141_data_out;
wire [7:0]fifo_150_data_out;
wire [7:0]fifo_151_data_out;
wire [7:0]fifo_160_data_out;
wire [7:0]fifo_161_data_out;
wire [7:0]fifo_170_data_out;
wire [7:0]fifo_171_data_out;


reg [287:0]first_sdr_data; 


assign user_output_data    = first_sdr_data;

always@(posedge clk90)
begin
    if (reset90_r == 1'b1)
    	first_sdr_data   <= 288'd0;
    else
    begin
             if (read_valid_data_1 == 1'b1)
               first_sdr_data  <= {fifo_170_data_out,fifo_160_data_out,
               				   fifo_150_data_out,fifo_140_data_out,
               				   fifo_130_data_out,fifo_120_data_out,
               				   fifo_110_data_out,fifo_100_data_out,
               				   fifo_90_data_out,fifo_80_data_out,