📄 data_read_controller.v
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// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay4_col1 (
.clk_in(dqs_int_delay_in4),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[4])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay5_col0 (
.clk_in(dqs_int_delay_in5),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[5])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay5_col1 (
.clk_in(dqs_int_delay_in5),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[5])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay6_col0 (
.clk_in(dqs_int_delay_in6),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[6])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay6_col1 (
.clk_in(dqs_int_delay_in6),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[6])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay7_col0 (
.clk_in(dqs_int_delay_in7),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[7])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay7_col1 (
.clk_in(dqs_int_delay_in7),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[7])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay8_col0 (
.clk_in(dqs_int_delay_in8),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[8])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay8_col1 (
.clk_in(dqs_int_delay_in8),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[8])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay9_col0 (
.clk_in(dqs_int_delay_in9),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[9])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay9_col1 (
.clk_in(dqs_int_delay_in9),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[9])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay10_col0 (
.clk_in(dqs_int_delay_in10),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[10])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay10_col1 (
.clk_in(dqs_int_delay_in10),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[10])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay11_col0 (
.clk_in(dqs_int_delay_in11),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[11])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay11_col1 (
.clk_in(dqs_int_delay_in11),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[11])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay12_col0 (
.clk_in(dqs_int_delay_in12),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[12])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay12_col1 (
.clk_in(dqs_int_delay_in12),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[12])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay13_col0 (
.clk_in(dqs_int_delay_in13),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[13])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay13_col1 (
.clk_in(dqs_int_delay_in13),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[13])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay14_col0 (
.clk_in(dqs_int_delay_in14),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[14])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay14_col1 (
.clk_in(dqs_int_delay_in14),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[14])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay15_col0 (
.clk_in(dqs_int_delay_in15),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[15])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay15_col1 (
.clk_in(dqs_int_delay_in15),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[15])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay16_col0 (
.clk_in(dqs_int_delay_in16),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[16])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay16_col1 (
.clk_in(dqs_int_delay_in16),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[16])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay17_col0 (
.clk_in(dqs_int_delay_in17),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[17])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay17_col1 (
.clk_in(dqs_int_delay_in17),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[17])
);
//****************************************************************************************************
// FIFO Write enable signal generation
//****************************************************************************************************
fifo_0_wr_en fifo_00_wr_en_inst (
.clk (dqs0_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div1),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.dout (fifo_00_wr_en)
);
fifo_1_wr_en fifo_01_wr_en_inst (
.clk (dqs0_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.reset (reset_r),
.din (rst_dqs_div1),
.dout (fifo_01_wr_en)
);
fifo_0_wr_en fifo_10_wr_en_inst (
.clk (dqs1_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div1),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.dout (fifo_10_wr_en)
);
fifo_1_wr_en fifo_11_wr_en_inst (
.clk (dqs1_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.reset (reset_r),
.din (rst_dqs_div1),
.dout (fifo_11_wr_en)
);
fifo_0_wr_en fifo_20_wr_en_inst (
.clk (dqs2_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div1),
.rst_dqs_delay_n (rst_dqs_delay_2_n),
.dout (fifo_20_wr_en)
);
fifo_1_wr_en fifo_21_wr_en_inst (
.clk (dqs2_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_2_n),
.reset (reset_r),
.din (rst_dqs_div1),
.dout (fifo_21_wr_en)
);
fifo_0_wr_en fifo_30_wr_en_inst (
.clk (dqs3_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div1),
.rst_dqs_delay_n (rst_dqs_delay_3_n),
.dout (fifo_30_wr_en)
);
fifo_1_wr_en fifo_31_wr_en_inst (
.clk (dqs3_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_3_n),
.reset (reset_r),
.din (rst_dqs_div1),
.dout (fifo_31_wr_en)
);
fifo_0_wr_en fifo_40_wr_en_inst (
.clk (dqs4_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div1),
.rst_dqs_delay_n (rst_dqs_delay_4_n),
.dout (fifo_40_wr_en)
);
fifo_1_wr_en fifo_41_wr_en_inst (
.clk (dqs4_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_4_n),
.reset (reset_r),
.din (rst_dqs_div1),
.dout (fifo_41_wr_en)
);
fifo_0_wr_en fifo_50_wr_en_inst (
.clk (dqs5_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div1),
.rst_dqs_delay_n (rst_dqs_delay_5_n),
.dout (fifo_50_wr_en)
);
fifo_1_wr_en fifo_51_wr_en_inst (
.clk (dqs5_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_5_n),
.reset (reset_r),
.din (rst_dqs_div1),
.dout (fifo_51_wr_en)
);
fifo_0_wr_en fifo_60_wr_en_inst (
.clk (dqs6_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div1),
.rst_dqs_delay_n (rst_dqs_delay_6_n),
.dout (fifo_60_wr_en)
);
fifo_1_wr_en fifo_61_wr_en_inst (
.clk (dqs6_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_6_n),
.reset (reset_r),
.din (rst_dqs_div1),
.dout (fifo_61_wr_en)
);
fifo_0_wr_en fifo_70_wr_en_inst (
.clk (dqs7_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div1),
.rst_dqs_delay_n (rst_dqs_delay_7_n),
.dout (fifo_70_wr_en)
);
fifo_1_wr_en fifo_71_wr_en_inst (
.clk (dqs7_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_7_n),
.reset (reset_r),
.din (rst_dqs_div1),
.dout (fifo_71_wr_en)
);
fifo_0_wr_en fifo_80_wr_en_inst (
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