📄 data_read_controller.v
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dqs_delay rst_dqs_div1_delayed (
.clk_in (rst_dqs_div_in1),
.sel_in (delay_sel),
.clk_out (rst_dqs_div1)
);
dqs_delay rst_dqs_div2_delayed (
.clk_in (rst_dqs_div_in2),
.sel_in (delay_sel),
.clk_out (rst_dqs_div2)
);
// fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )
rd_gray_cntr fifo_00_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_00_rd_addr)
);
rd_gray_cntr fifo_01_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_01_rd_addr)
);
rd_gray_cntr fifo_10_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_10_rd_addr)
);
rd_gray_cntr fifo_11_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_11_rd_addr)
);
rd_gray_cntr fifo_20_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_20_rd_addr)
);
rd_gray_cntr fifo_21_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_21_rd_addr)
);
rd_gray_cntr fifo_30_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_30_rd_addr)
);
rd_gray_cntr fifo_31_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_31_rd_addr)
);
rd_gray_cntr fifo_40_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_40_rd_addr)
);
rd_gray_cntr fifo_41_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_41_rd_addr)
);
rd_gray_cntr fifo_50_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_50_rd_addr)
);
rd_gray_cntr fifo_51_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_51_rd_addr)
);
rd_gray_cntr fifo_60_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_60_rd_addr)
);
rd_gray_cntr fifo_61_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_61_rd_addr)
);
rd_gray_cntr fifo_70_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_70_rd_addr)
);
rd_gray_cntr fifo_71_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_71_rd_addr)
);
rd_gray_cntr fifo_80_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_80_rd_addr)
);
rd_gray_cntr fifo_81_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_81_rd_addr)
);
rd_gray_cntr fifo_90_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_90_rd_addr)
);
rd_gray_cntr fifo_91_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_91_rd_addr)
);
rd_gray_cntr fifo_100_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_100_rd_addr)
);
rd_gray_cntr fifo_101_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_101_rd_addr)
);
rd_gray_cntr fifo_110_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_110_rd_addr)
);
rd_gray_cntr fifo_111_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_111_rd_addr)
);
rd_gray_cntr fifo_120_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_120_rd_addr)
);
rd_gray_cntr fifo_121_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_121_rd_addr)
);
rd_gray_cntr fifo_130_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_130_rd_addr)
);
rd_gray_cntr fifo_131_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_131_rd_addr)
);
rd_gray_cntr fifo_140_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_140_rd_addr)
);
rd_gray_cntr fifo_141_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_141_rd_addr)
);
rd_gray_cntr fifo_150_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_150_rd_addr)
);
rd_gray_cntr fifo_151_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_151_rd_addr)
);
rd_gray_cntr fifo_160_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_160_rd_addr)
);
rd_gray_cntr fifo_161_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_161_rd_addr)
);
rd_gray_cntr fifo_170_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_170_rd_addr)
);
rd_gray_cntr fifo_171_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_171_rd_addr)
);
//-------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------------------------------------------------
//**************************************************************************************************
// DQS Internal Delay Circuit implemented in LUTs
//**************************************************************************************************
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay0_col0 (
.clk_in(dqs_int_delay_in0),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[0])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay0_col1 (
.clk_in(dqs_int_delay_in0),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[0])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay1_col0 (
.clk_in(dqs_int_delay_in1),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[1])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay1_col1 (
.clk_in(dqs_int_delay_in1),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[1])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay2_col0 (
.clk_in(dqs_int_delay_in2),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[2])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay2_col1 (
.clk_in(dqs_int_delay_in2),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[2])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay3_col0 (
.clk_in(dqs_int_delay_in3),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[3])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay3_col1 (
.clk_in(dqs_int_delay_in3),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[3])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay4_col0 (
.clk_in(dqs_int_delay_in4),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[4])
);
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