data_read_controller.v

XILINX memory interface generator. XILINX的外部存储器接口。

output     fifo_151_wr_en_val;			  		  
output     fifo_161_wr_en_val;			  
output     fifo_171_wr_en_val;			  


output     [3:0]fifo_00_wr_addr_val;   
output     [3:0]fifo_01_wr_addr_val;    
output     [3:0]fifo_10_wr_addr_val;    
output     [3:0]fifo_11_wr_addr_val;    
output     [3:0]fifo_20_wr_addr_val;    
output     [3:0]fifo_21_wr_addr_val;    
output     [3:0]fifo_30_wr_addr_val;    
output     [3:0]fifo_31_wr_addr_val;    
output     [3:0]fifo_40_wr_addr_val;   
output     [3:0]fifo_41_wr_addr_val;    
output     [3:0]fifo_50_wr_addr_val;    
output     [3:0]fifo_51_wr_addr_val;    
output     [3:0]fifo_60_wr_addr_val;    
output     [3:0]fifo_61_wr_addr_val;    
output     [3:0]fifo_70_wr_addr_val;    
output     [3:0]fifo_71_wr_addr_val;    
output     [3:0]fifo_80_wr_addr_val;    
output     [3:0]fifo_81_wr_addr_val;   
output     [3:0]fifo_90_wr_addr_val;    
output     [3:0]fifo_91_wr_addr_val;   
output     [3:0]fifo_100_wr_addr_val;   
output     [3:0]fifo_101_wr_addr_val;    
output     [3:0]fifo_110_wr_addr_val;    
output     [3:0]fifo_111_wr_addr_val;    
output     [3:0]fifo_120_wr_addr_val;    
output     [3:0]fifo_121_wr_addr_val;    
output     [3:0]fifo_130_wr_addr_val;    
output     [3:0]fifo_131_wr_addr_val;    
output     [3:0]fifo_140_wr_addr_val;   
output     [3:0]fifo_141_wr_addr_val;    
output     [3:0]fifo_150_wr_addr_val;    
output     [3:0]fifo_151_wr_addr_val;    
output     [3:0]fifo_160_wr_addr_val;    
output     [3:0]fifo_161_wr_addr_val;    
output     [3:0]fifo_170_wr_addr_val;    
output     [3:0]fifo_171_wr_addr_val;    

     
output     dqs0_delayed_col1_val; 
output     dqs1_delayed_col1_val; 
output     dqs2_delayed_col1_val;  
output     dqs3_delayed_col1_val;  
output     dqs4_delayed_col1_val; 
output     dqs5_delayed_col1_val;  
output     dqs6_delayed_col1_val; 
output     dqs7_delayed_col1_val; 
output     dqs8_delayed_col1_val;  
output     dqs9_delayed_col1_val;
output     dqs10_delayed_col1_val; 
output     dqs11_delayed_col1_val; 
output     dqs12_delayed_col1_val;  
output     dqs13_delayed_col1_val;  
output     dqs14_delayed_col1_val; 
output     dqs15_delayed_col1_val;  
output     dqs16_delayed_col1_val; 
output     dqs17_delayed_col1_val; 

  

output     dqs0_delayed_col0_n_val;
output     dqs1_delayed_col0_n_val;
output     dqs2_delayed_col0_n_val;
output     dqs3_delayed_col0_n_val;
output     dqs4_delayed_col0_n_val;
output     dqs5_delayed_col0_n_val;
output     dqs6_delayed_col0_n_val;
output     dqs7_delayed_col0_n_val;
output     dqs8_delayed_col0_n_val;
output     dqs9_delayed_col0_n_val;
output     dqs10_delayed_col0_n_val;
output     dqs11_delayed_col0_n_val;
output     dqs12_delayed_col0_n_val;
output     dqs13_delayed_col0_n_val;
output     dqs14_delayed_col0_n_val;
output     dqs15_delayed_col0_n_val;
output     dqs16_delayed_col0_n_val;
output     dqs17_delayed_col0_n_val;


reg        u_data_val;

wire dqs_int_delay_in0;
wire dqs_int_delay_in1;
wire dqs_int_delay_in2;
wire dqs_int_delay_in3;
wire dqs_int_delay_in4;
wire dqs_int_delay_in5;
wire dqs_int_delay_in6;
wire dqs_int_delay_in7;
wire dqs_int_delay_in8;
wire dqs_int_delay_in9;
wire dqs_int_delay_in10;
wire dqs_int_delay_in11;
wire dqs_int_delay_in12;
wire dqs_int_delay_in13;
wire dqs_int_delay_in14;
wire dqs_int_delay_in15;
wire dqs_int_delay_in16;
wire dqs_int_delay_in17;


wire [17:0]dqs_delayed_col0;
wire [17:0]dqs_delayed_col1;
wire resetn;


wire fifo_00_empty;
wire fifo_01_empty;


wire [3:0] fifo_00_wr_addr;
wire [3:0] fifo_01_wr_addr;
wire [3:0] fifo_10_wr_addr;
wire [3:0] fifo_11_wr_addr;
wire [3:0] fifo_20_wr_addr;
wire [3:0] fifo_21_wr_addr;
wire [3:0] fifo_30_wr_addr;
wire [3:0] fifo_31_wr_addr;
wire [3:0] fifo_40_wr_addr;
wire [3:0] fifo_41_wr_addr;
wire [3:0] fifo_50_wr_addr;
wire [3:0] fifo_51_wr_addr;
wire [3:0] fifo_60_wr_addr;
wire [3:0] fifo_61_wr_addr;
wire [3:0] fifo_70_wr_addr;
wire [3:0] fifo_71_wr_addr;
wire [3:0] fifo_80_wr_addr;
wire [3:0] fifo_81_wr_addr;
wire [3:0] fifo_90_wr_addr;
wire [3:0] fifo_91_wr_addr;
wire [3:0] fifo_100_wr_addr;
wire [3:0] fifo_101_wr_addr;
wire [3:0] fifo_110_wr_addr;
wire [3:0] fifo_111_wr_addr;
wire [3:0] fifo_120_wr_addr;
wire [3:0] fifo_121_wr_addr;
wire [3:0] fifo_130_wr_addr;
wire [3:0] fifo_131_wr_addr;
wire [3:0] fifo_140_wr_addr;
wire [3:0] fifo_141_wr_addr;
wire [3:0] fifo_150_wr_addr;
wire [3:0] fifo_151_wr_addr;
wire [3:0] fifo_160_wr_addr;
wire [3:0] fifo_161_wr_addr;
wire [3:0] fifo_170_wr_addr;
wire [3:0] fifo_171_wr_addr;


wire read_valid_data_0_1;
wire read_valid_data_1; 



//wire reset_r; 
//wire reset90_r;
//wire reset180_r;
//wire reset270_r;

wire dqs0_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs1_delayed_col0/* synthesis syn_keep=1 */;
wire dqs2_delayed_col0/* synthesis syn_keep=1 */;
wire dqs3_delayed_col0/* synthesis syn_keep=1 */;
wire dqs4_delayed_col0/* synthesis syn_keep=1 */;
wire dqs5_delayed_col0/* synthesis syn_keep=1 */;
wire dqs6_delayed_col0/* synthesis syn_keep=1 */;
wire dqs7_delayed_col0/* synthesis syn_keep=1 */;
wire dqs8_delayed_col0/* synthesis syn_keep=1 */;
wire dqs9_delayed_col0/* synthesis syn_keep=1 */;
wire dqs10_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs11_delayed_col0/* synthesis syn_keep=1 */;
wire dqs12_delayed_col0/* synthesis syn_keep=1 */;
wire dqs13_delayed_col0/* synthesis syn_keep=1 */;
wire dqs14_delayed_col0/* synthesis syn_keep=1 */;
wire dqs15_delayed_col0/* synthesis syn_keep=1 */;
wire dqs16_delayed_col0/* synthesis syn_keep=1 */;
wire dqs17_delayed_col0/* synthesis syn_keep=1 */;


wire dqs0_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs1_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs2_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs3_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs4_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs5_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs6_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs7_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs8_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs9_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs10_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs11_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs12_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs13_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs14_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs15_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs16_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs17_delayed_col1 /* synthesis syn_keep=1 */;	



wire dqs0_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs1_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs2_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs3_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs4_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs5_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs6_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs7_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs8_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs9_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs10_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs11_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs12_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs13_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs14_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs15_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs16_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs17_delayed_col0_n /* synthesis syn_keep=1 */;


wire dqs0_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs1_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs2_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs3_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs4_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs5_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs6_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs7_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs8_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs9_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs10_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs11_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs12_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs13_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs14_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs15_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs16_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs17_delayed_col1_n /* synthesis syn_keep=1 */;


wire 	   TIE_HIGH;


// FIFO WRITE ENABLE SIGNALS

wire 	fifo_00_wr_en;
wire 	fifo_01_wr_en;
wire 	fifo_10_wr_en;
wire 	fifo_11_wr_en;
wire 	fifo_20_wr_en;
wire 	fifo_21_wr_en;
wire 	fifo_30_wr_en;
wire 	fifo_31_wr_en;
wire 	fifo_40_wr_en;
wire 	fifo_41_wr_en;
wire 	fifo_50_wr_en;
wire 	fifo_51_wr_en;
wire 	fifo_60_wr_en;
wire 	fifo_61_wr_en;
wire 	fifo_70_wr_en;
wire 	fifo_71_wr_en;
wire 	fifo_80_wr_en;
wire 	fifo_81_wr_en;
wire 	fifo_90_wr_en;
wire 	fifo_91_wr_en;
wire 	fifo_100_wr_en;
wire 	fifo_101_wr_en;
wire 	fifo_110_wr_en;
wire 	fifo_111_wr_en;
wire 	fifo_120_wr_en;
wire 	fifo_121_wr_en;
wire 	fifo_130_wr_en;
wire 	fifo_131_wr_en;
wire 	fifo_140_wr_en;
wire 	fifo_141_wr_en;
wire 	fifo_150_wr_en;
wire 	fifo_151_wr_en;
wire 	fifo_160_wr_en;
wire 	fifo_161_wr_en;
wire 	fifo_170_wr_en;
wire 	fifo_171_wr_en;



//signal rst_dqs_delay_n : std_logic;
wire rst_dqs_delay_0_n;
wire rst_dqs_delay_1_n;
wire rst_dqs_delay_2_n;
wire rst_dqs_delay_3_n;
wire rst_dqs_delay_4_n;
wire rst_dqs_delay_5_n;
wire rst_dqs_delay_6_n;
wire rst_dqs_delay_7_n;
wire rst_dqs_delay_8_n;
wire rst_dqs_delay_9_n;
wire rst_dqs_delay_10_n;
wire rst_dqs_delay_11_n;
wire rst_dqs_delay_12_n;
wire rst_dqs_delay_13_n;
wire rst_dqs_delay_14_n;
wire rst_dqs_delay_15_n;
wire rst_dqs_delay_16_n;
wire rst_dqs_delay_17_n;

// FIFO_WR_POINTER Delayed signals in clk90 domain

wire [3:0]fifo_00_rd_addr;
wire [3:0]fifo_01_rd_addr;
wire [3:0]fifo_10_rd_addr;
wire [3:0]fifo_11_rd_addr;
wire [3:0]fifo_20_rd_addr;
wire [3:0]fifo_21_rd_addr;
wire [3:0]fifo_30_rd_addr;
wire [3:0]fifo_31_rd_addr;
wire [3:0]fifo_40_rd_addr;
wire [3:0]fifo_41_rd_addr;
wire [3:0]fifo_50_rd_addr;
wire [3:0]fifo_51_rd_addr;