data_write.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
module data_write (

     user_input_data,    
     clk90,              
     reset90_r,          
     reset270_r,         
     write_enable,       
     write_en_val,       
     write_data_falling, 
     write_data_rising,  
     data_mask_f,
     data_mask_r
     );


input     [287:0]user_input_data;
input     clk90;              
input     reset90_r;          
input     reset270_r;         
input     write_enable;       
output    write_en_val;       
output    [143:0]write_data_falling; 
output    [143:0]write_data_rising;  
output    [17:0]data_mask_f;        
output    [17:0]data_mask_r;   

reg write_en_val;

reg write_en_P1;          
reg write_en_P2;          
reg write_en_P3;          
reg write_en_int;         
reg [287:0]write_data;    
reg [287:0]write_data1;   
reg [287:0]write_data2;   
reg [287:0]write_data3;   
reg [287:0]write_data4;   
reg [287:0]write_data5;   
reg [287:0]write_data6;   
reg [287:0]write_data_int;
reg [143:0]write_data270_1;
reg [143:0]write_data270_2;
  
  
  
assign data_mask_f = 18'd0;
assign data_mask_r = 18'd0;
     
always@(posedge clk90)
begin
    if (reset90_r == 1'b1)
    begin
       write_data_int   <= 288'd0;
       write_data1      <= 288'd0;
       write_data2      <= 288'd0;
       write_data3      <= 288'd0;
       write_data4      <= 288'd0;
       write_data5      <= 288'd0;
       write_data6      <= 288'd0;
       write_data       <= 288'd0;
    end
    else
    begin
       write_data_int         <= user_input_data;
       write_data1            <= write_data_int;
       write_data2            <= write_data1;
       write_data3            <= write_data2;
       write_data4            <= write_data3;
       write_data5            <= write_data4;
       write_data6            <= write_data5;
       write_data             <= write_data6;
     end
end

always@(negedge clk90)
begin
   if (reset270_r == 1'b1)
   	begin
        write_data270_1  <= 144'd0;
        write_data270_2  <= 144'd0;
        end
   else
   	begin 
        write_data270_1  <= write_data5[287:144];
        write_data270_2  <= write_data270_1;
         end 
end

assign write_data_rising  = write_data270_2;
assign write_data_falling = write_data[143:0];


////--------------------------------------------------------------------------------
// data path for write enable
always@(posedge clk90)
begin
   if(reset90_r== 1'b1)
   begin
    	write_en_P1 <= 1'b0;
    	write_en_P2 <= 1'b0;
    	write_en_P3 <= 1'b0;
   end
   else
   begin 
        write_en_P1 <= write_enable;
        write_en_P2 <= write_en_P1;
        write_en_P3 <= write_en_P2;
    end    
end

always@(negedge clk90)
begin
  if (reset90_r == 1'b1)
  	begin
        write_en_int    <= 1'b0;
        write_en_val    <= 1'b0;
 
        end
  else
  	begin
     	write_en_int   <= write_en_P2;//P2
     	write_en_val   <= write_en_int; //int;
 
 	end
end

endmodule