📄 data_path_iobs.v
字号:
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob61
(
.ddr_dq_inout (ddr_dq[61]),
.write_data_falling (write_data_falling[61]),
.write_data_rising (write_data_rising[61]),
.read_data_in (ddr_dq_in[61]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob62
(
.ddr_dq_inout (ddr_dq[62]),
.write_data_falling (write_data_falling[62]),
.write_data_rising (write_data_rising[62]),
.read_data_in (ddr_dq_in[62]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob63
(
.ddr_dq_inout (ddr_dq[63]),
.write_data_falling (write_data_falling[63]),
.write_data_rising (write_data_rising[63]),
.read_data_in (ddr_dq_in[63]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob64
(
.ddr_dq_inout (ddr_dq[64]),
.write_data_falling (write_data_falling[64]),
.write_data_rising (write_data_rising[64]),
.read_data_in (ddr_dq_in[64]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob65
(
.ddr_dq_inout (ddr_dq[65]),
.write_data_falling (write_data_falling[65]),
.write_data_rising (write_data_rising[65]),
.read_data_in (ddr_dq_in[65]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob66
(
.ddr_dq_inout (ddr_dq[66]),
.write_data_falling (write_data_falling[66]),
.write_data_rising (write_data_rising[66]),
.read_data_in (ddr_dq_in[66]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob67
(
.ddr_dq_inout (ddr_dq[67]),
.write_data_falling (write_data_falling[67]),
.write_data_rising (write_data_rising[67]),
.read_data_in (ddr_dq_in[67]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob68
(
.ddr_dq_inout (ddr_dq[68]),
.write_data_falling (write_data_falling[68]),
.write_data_rising (write_data_rising[68]),
.read_data_in (ddr_dq_in[68]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob69
(
.ddr_dq_inout (ddr_dq[69]),
.write_data_falling (write_data_falling[69]),
.write_data_rising (write_data_rising[69]),
.read_data_in (ddr_dq_in[69]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob70
(
.ddr_dq_inout (ddr_dq[70]),
.write_data_falling (write_data_falling[70]),
.write_data_rising (write_data_rising[70]),
.read_data_in (ddr_dq_in[70]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob71
(
.ddr_dq_inout (ddr_dq[71]),
.write_data_falling (write_data_falling[71]),
.write_data_rising (write_data_rising[71]),
.read_data_in (ddr_dq_in[71]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob72
(
.ddr_dq_inout (ddr_dq[72]),
.write_data_falling (write_data_falling[72]),
.write_data_rising (write_data_rising[72]),
.read_data_in (ddr_dq_in[72]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob73
(
.ddr_dq_inout (ddr_dq[73]),
.write_data_falling (write_data_falling[73]),
.write_data_rising (write_data_rising[73]),
.read_data_in (ddr_dq_in[73]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob74
(
.ddr_dq_inout (ddr_dq[74]),
.write_data_falling (write_data_falling[74]),
.write_data_rising (write_data_rising[74]),
.read_data_in (ddr_dq_in[74]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob75
(
.ddr_dq_inout (ddr_dq[75]),
.write_data_falling (write_data_falling[75]),
.write_data_rising (write_data_rising[75]),
.read_data_in (ddr_dq_in[75]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob76
(
.ddr_dq_inout (ddr_dq[76]),
.write_data_falling (write_data_falling[76]),
.write_data_rising (write_data_rising[76]),
.read_data_in (ddr_dq_in[76]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob77
(
.ddr_dq_inout (ddr_dq[77]),
.write_data_falling (write_data_falling[77]),
.write_data_rising (write_data_rising[77]),
.read_data_in (ddr_dq_in[77]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob78
(
.ddr_dq_inout (ddr_dq[78]),
.write_data_falling (write_data_falling[78]),
.write_data_rising (write_data_rising[78]),
.read_data_in (ddr_dq_in[78]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob79
(
.ddr_dq_inout (ddr_dq[79]),
.write_data_falling (write_data_falling[79]),
.write_data_rising (write_data_rising[79]),
.read_data_in (ddr_dq_in[79]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob80
(
.ddr_dq_inout (ddr_dq[80]),
.write_data_falling (write_data_falling[80]),
.write_data_rising (write_data_rising[80]),
.read_data_in (ddr_dq_in[80]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob81
(
.ddr_dq_inout (ddr_dq[81]),
.write_data_falling (write_data_falling[81]),
.write_data_rising (write_data_rising[81]),
.read_data_in (ddr_dq_in[81]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob82
(
.ddr_dq_inout (ddr_dq[82]),
.write_data_falling (write_data_falling[82]),
.write_data_rising (write_data_rising[82]),
.read_data_in (ddr_dq_in[82]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob83
(
.ddr_dq_inout (ddr_dq[83]),
.write_data_falling (write_data_falling[83]),
.write_data_rising (write_data_rising[83]),
.read_data_in (ddr_dq_in[83]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob84
(
.ddr_dq_inout (ddr_dq[84]),
.write_data_falling (write_data_falling[84]),
.write_data_rising (write_data_rising[84]),
.read_data_in (ddr_dq_in[84]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob85
(
.ddr_dq_inout (ddr_dq[85]),
.write_data_falling (write_data_falling[85]),
.write_data_rising (write_data_rising[85]),
.read_data_in (ddr_dq_in[85]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob86
(
.ddr_dq_inout (ddr_dq[86]),
.write_data_falling (write_data_falling[86]),
.write_data_rising (write_data_rising[86]),
.read_data_in (ddr_dq_in[86]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob87
(
.ddr_dq_inout (ddr_dq[87]),
.write_data_falling (write_data_falling[87]),
.write_data_rising (write_data_rising[87]),
.read_data_in (ddr_dq_in[87]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob88
(
.ddr_dq_inout (ddr_dq[88]),
.write_data_falling (write_data_falling[88]),
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