infrastructure_top.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--

entity infrastructure_top is
  port(
       reset_in         : in std_logic;
--NO_DCM     clk_int    : in std_logic;
--NO_DCM     clk90_int  : in std_logic;
--NO_DCM     dcm_lock   : in std_logic;
             sys_clk_ibuf     : in std_logic;
       delay_sel_val1_val_tb : out std_logic_vector(4 downto 0);
       delay_sel_val1_val_rl : out std_logic_vector(4 downto 0);
       sys_rst_val          : out std_logic;
       sys_rst90_val        : out std_logic;
--YES_DCM       clk_int_val          : out std_logic;
--YES_DCM      clk90_int_val        : out std_logic;
       sys_rst180_val       : out std_logic;
       sys_rst270_val       : out std_logic;
	 wait_200us           : out std_logic
  );
  
end   infrastructure_top;

architecture arc_infrastructure_top of infrastructure_top is

---- Component declarations -----

--YES_DCM component clk_dcm 
--YES_DCM port(
--YES_DCM      input_clk   : in std_logic;
--YES_DCM      rst         : in std_logic;
--YES_DCM      clk         : out std_logic;
--YES_DCM      clk90       : out std_logic;
--YES_DCM      dcm_lock    : out std_logic
--YES_DCM      );
--YES_DCM end component;

component cal_top                                                 
port             (                                                
	          clk          : in std_logic;                     
	          clk0dcmlock  : in std_logic;                     
	          reset        : in std_logic;                     
	          okToSelTap   : in std_logic;
	          tapForDqs_tb : out std_logic_vector(4 downto 0);
	          tapForDqs_rl : out std_logic_vector(4 downto 0)
                 );                                               
end component;

---- Signal declarations used on the diagram ----

signal user_rst                : std_logic;
--YES_DCM signal clk_int                 : std_logic;
--YES_DCM signal clk90_int               : std_logic;
--YES_DCM signal dcm_lock                : std_logic;
signal sys_rst_o               : std_logic;
signal sys_rst_1               : std_logic := '1';
signal sys_rst                 : std_logic ;
signal sys_rst90_o             : std_logic;
signal sys_rst90_1             : std_logic := '1';
signal sys_rst90               : std_logic;
signal sys_rst180_o            : std_logic;
signal sys_rst180_1            : std_logic := '1';
signal sys_rst180              : std_logic ;
signal sys_rst270_o            : std_logic;
signal sys_rst270_1            : std_logic := '1';
signal sys_rst270              : std_logic ;
signal delay_sel_val           : std_logic_vector(4 downto 0);
signal delay_sel_val1_tb       : std_logic_vector(4 downto 0);
signal delay_sel_val1_rl       : std_logic_vector(4 downto 0);
signal delay_sel_val1_r        : std_logic_vector(4 downto 0);
signal rst_calib1_r1           : std_logic;
signal rst_calib1_r2           : std_logic;
signal stuck_at1               : std_logic;
signal vcc                     : std_logic;

signal clk_int_val1            : std_logic;
signal clk_int_val2            : std_logic;
signal clk90_int_val1          : std_logic;
signal clk90_int_val2          : std_logic;

signal  wait_200us_i             : std_logic;
signal  wait_clk90            : std_logic;
signal  Counter200               : std_logic_vector(15 downto 0);


begin

--YES_DCM clk_int_val <= clk_int;
--YES_DCM clk90_int_val <= clk90_int;


sys_rst_val <= sys_rst;
sys_rst90_val <= sys_rst90;
sys_rst180_val <= sys_rst180;
sys_rst270_val <= sys_rst270;

delay_sel_val1_val_tb <= delay_sel_val1_tb;
delay_sel_val1_val_rl <= delay_sel_val1_rl;


-----   To remove delta delays in the clock signals observed during simulation ,Following signals are used 

clk_int_val1 <= clk_int;
clk90_int_val1 <= clk90_int;
clk_int_val2 <= clk_int_val1;
clk90_int_val2 <= clk90_int_val1;
vcc       <= '1';
user_rst  <= not reset_in;                                        

--delay_sel_val1 <= delay_sel_val when (rst_calib1 = '0' and rst_calib1_r2 = '0') else
--                  delay_sel_val1_r;


wait_200us <= wait_200us_i;
--For 200us during power up
process(clk_int_val2)
begin
 if clk_int_val2'event and clk_int_val2 = '1' then
  if user_rst = '1' or dcm_lock = '0' then
     wait_200us_i     <= '1';
     Counter200       <= (others => '0');
  else
      if( Counter200(15) = '1' and Counter200(13) = '1' and wait_200us_i = '1') then--(THIS IS DIFFERENT IN DDR2)
         wait_200us_i <='0';
      elsif (wait_200us_i = '1') then
         Counter200 <= Counter200 + 1;
      else    
         Counter200 <= Counter200;
     end if;
  end if;
 end if;
end process;


process(clk90_int_val2)
begin
 if clk90_int_val2'event and clk90_int_val2 = '1' then
  if user_rst = '1' or dcm_lock = '0' then
      wait_clk90 <= '1';
   else
      wait_clk90 <= wait_200us_i;
  end if;
 end if;
end process;



process(clk_int_val2)
begin
 if clk_int_val2'event and clk_int_val2 = '1' then
  if user_rst = '1' or dcm_lock = '0' or wait_200us_i = '1' then
      sys_rst_o <= '1';
      sys_rst_1 <= '1';
      sys_rst   <= '1';
  else
      sys_rst_o <= '0';
      sys_rst_1 <= sys_rst_o;
      sys_rst   <= sys_rst_1;
  end if;
 end if;
end process;


process(clk90_int_val2)
begin
 if clk90_int_val2'event and clk90_int_val2 = '1' then
  if user_rst = '1' or dcm_lock = '0' or wait_clk90 = '1' then
      sys_rst90_o <= '1';
      sys_rst90_1 <= '1';
      sys_rst90   <= '1';
  else
      sys_rst90_o <= '0';
      sys_rst90_1 <= sys_rst90_o;
      sys_rst90   <= sys_rst90_1;
  end if;
 end if;
end process;

process(clk_int_val2)
begin
 if clk_int_val2'event and clk_int_val2 = '0' then
  if user_rst = '1' or dcm_lock = '0' or wait_200us_i = '1' then
      sys_rst180_o <= '1';
      sys_rst180_1 <= '1';
      sys_rst180   <= '1';
  else
      sys_rst180_o <= '0';
      sys_rst180_1 <= sys_rst180_o;
      sys_rst180   <= sys_rst180_1;
  end if;
 end if;
end process;

process(clk90_int_val2)
begin
 if clk90_int_val2'event and clk90_int_val2 = '0' then
  if user_rst = '1' or dcm_lock = '0' or wait_clk90 = '1' then
      sys_rst270_o <= '1';
      sys_rst270_1 <= '1';
      sys_rst270   <= '1';
  else
      sys_rst270_o <= '0';
      sys_rst270_1 <= sys_rst270_o;
      sys_rst270   <= sys_rst270_1;
  end if;
 end if;
end process;

----  Component instantiations  ----

                                   
--YES_DCM clk_dcm0 : clk_dcm port map (
--YES_DCM                              input_clk   => sys_clk_ibuf,
--YES_DCM                              rst         => user_rst,                            
--YES_DCM                              clk         => clk_int,
--YES_DCM                              clk90       => clk90_int,
--YES_DCM                              dcm_lock    => dcm_lock
--YES_DCM                             ); 
                            
cal_top0 : cal_top port map (                                                 
                         
                             clk          => clk_int_val2,          
                             clk0dcmlock  => dcm_lock,  
                             reset        => reset_in,      
                             okToSelTap   => vcc,
                             tapForDqs_tb => delay_sel_val1_tb,
                             tapForDqs_rl => delay_sel_val1_rl
                             );       
                                          

end arc_infrastructure_top;