infrastructure.vhd

来自「XILINX memory interface generator. XILI」· VHDL 代码 · 共 71 行

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--

entity infrastructure is
  port(
       delay_sel_val1_val   : out std_logic_vector(4 downto 0);
       delay_sel_val     : in std_logic_vector(4 downto 0);
       rst_calib1       : in std_logic;
       sys_rst          : in std_logic;
       clk_int          : in std_logic
  );
end   infrastructure;

architecture arc_infrastructure of infrastructure is

---- Component declarations -----


---- Signal declarations used on the diagram ----

signal user_rst                : std_logic;
signal dcm_lock                : std_logic;
--signal delay_sel_val           : std_logic_vector(4 downto 0);
signal delay_sel_val1          : std_logic_vector(4 downto 0);
signal delay_sel_val1_r        : std_logic_vector(4 downto 0);
signal rst_calib1_r1           : std_logic;
signal rst_calib1_r2           : std_logic;

begin

delay_sel_val1_val <= delay_sel_val1;


-----   To remove delta delays in the clock signals observed during simulation ,Following signals are used 

--vcc       <= '1';
--user_rst  <= not reset_in;                                        

delay_sel_val1 <= delay_sel_val when (rst_calib1 = '0' and rst_calib1_r2 = '0') else
                  delay_sel_val1_r;


process(clk_int)
begin
 if clk_int 'event and clk_int = '1' then
   if sys_rst = '1' then
     delay_sel_val1_r <= "00000";
     rst_calib1_r1    <= '0';
     rst_calib1_r2    <= '0';
   else
     delay_sel_val1_r <= delay_sel_val1;
     rst_calib1_r1    <= rst_calib1;
     rst_calib1_r2    <= rst_calib1_r1;
   end if;
 end if;
end process;


end arc_infrastructure;