tap_dly.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

			   Q => flop1(5),
			   C => clk,
			   D => tap(5),
			   R => reset 	
			  );

r6  : FDR port map  (
			   Q => flop1(6),
			   C => clk,
			   D => tap(6),
			   R => reset 	
			  );

r7  : FDR port map  (
			   Q => flop1(7),
			   C => clk,
			   D => tap(7),
			   R => reset 	
			  );

r8  : FDR port map  (
			   Q => flop1(8),
			   C => clk,
			   D => tap(8),
			   R => reset 	
			  );

r9  : FDR port map  (
			   Q => flop1(9),
			   C => clk,
			   D => tap(9),
			   R => reset 	
			  );

r10  : FDR port map  (
			   Q => flop1(10),
			   C => clk,
			   D => tap(10),
			   R => reset 	
			  );

r11  : FDR port map  (
			   Q => flop1(11),
			   C => clk,
			   D => tap(11),
			   R => reset 	
			  );

r12  : FDR port map  (
			   Q => flop1(12),
			   C => clk,
			   D => tap(12),
			   R => reset 	
			  );

r13  : FDR port map  (
			   Q => flop1(13),
			   C => clk,
			   D => tap(13),
			   R => reset 	
			  );

r14  : FDR port map  (
			   Q => flop1(14),
			   C => clk,
			   D => tap(14),
			   R => reset 	
			  );

r15  : FDR port map  (
			   Q => flop1(15),
			   C => clk,
			   D => tap(15),
			   R => reset 	
			  );

r16  : FDR port map  (
			   Q => flop1(16),
			   C => clk,
			   D => tap(16),
			   R => reset 	
			  );

r17  : FDR port map  (
			   Q => flop1(17),
			   C => clk,
			   D => tap(17),
			   R => reset 	
			  );

r18  : FDR port map  (
			   Q => flop1(18),
			   C => clk,
			   D => tap(18),
			   R => reset 	
			  );

r19  : FDR port map  (
			   Q => flop1(19),
			   C => clk,
			   D => tap(19),
			   R => reset 	
			  );

r20  : FDR port map  (
			   Q => flop1(20),
			   C => clk,
			   D => tap(20),
			   R => reset 	
			  );

r21  : FDR port map  (
			   Q => flop1(21),
			   C => clk,
			   D => tap(21),
			   R => reset 	
			  );

r22  : FDR port map  (
			   Q => flop1(22),
			   C => clk,
			   D => tap(22),
			   R => reset 	
			  );

r23  : FDR port map  (
			   Q => flop1(23),
			   C => clk,
			   D => tap(23),
			   R => reset 	
			  );

r24  : FDR port map  (
			   Q => flop1(24),
			   C => clk,
			   D => tap(24),
			   R => reset 	
			  );

r25  : FDR port map  (
			   Q => flop1(25),
			   C => clk,
			   D => tap(25),
			   R => reset 	
			  );

r26  : FDR port map  (
			   Q => flop1(26),
			   C => clk,
			   D => tap(26),
			   R => reset 	
			  );

r27  : FDR port map  (
			   Q => flop1(27),
			   C => clk,
			   D => tap(27),
			   R => reset 	
			  );

r28  : FDR port map  (
			   Q => flop1(28),
			   C => clk,
			   D => tap(28),
			   R => reset 	
			  );

r29  : FDR port map  (
			   Q => flop1(29),
			   C => clk,
			   D => tap(29),
			   R => reset 	
			  );

r30  : FDR port map  (
			   Q => flop1(30),
			   C => clk,
			   D => tap(30),
			   R => reset 	
			  );

r31  : FDR port map  (
			   Q => flop1(31),
			   C => clk,
			   D => tap(31),
			   R => reset 	
			  );

u0  : FDR port map  (
			   Q => flop2n_0,
			   C => clk,
			   D => flop1(0),
			   R => reset 	
			  );

u1  : FDR port map  (
			   Q => flop2(1),
			   C => clk,
			   D => flop1(1),
			   R => reset 	
			  );

u2  : FDR port map  (
			   Q => flop2n_2,
			   C => clk,
			   D => flop1(2),
			   R => reset 	
			  );

u3  : FDR port map  (
			   Q => flop2(3),
			   C => clk,
			   D => flop1(3),
			   R => reset 	
			  );

u4  : FDR port map  (
			   Q => flop2n_4,
			   C => clk,
			   D => flop1(4),
			   R => reset 	
			  );

u5  : FDR port map  (
			   Q => flop2(5),
			   C => clk,
			   D => flop1(5),
			   R => reset 	
			  );

u6  : FDR port map  (
			   Q => flop2n_6,
			   C => clk,
			   D => flop1(6),
			   R => reset 	
			  );

u7  : FDR port map  (
			   Q => flop2(7),
			   C => clk,
			   D => flop1(7),
			   R => reset 	
			  );

u8  : FDR port map  (
			   Q => flop2n_8,
			   C => clk,
			   D => flop1(8),
			   R => reset 	
			  );

u9  : FDR port map  (
			   Q => flop2(9),
			   C => clk,
			   D => flop1(9),
			   R => reset 	
			  );

u10  : FDR port map  (
			   Q => flop2n_10,
			   C => clk,
			   D => flop1(10),
			   R => reset 	
			  );

u11  : FDR port map  (
			   Q => flop2(11),
			   C => clk,
			   D => flop1(11),
			   R => reset 	
			  );

u12  : FDR port map  (
			   Q => flop2n_12,
			   C => clk,
			   D => flop1(12),
			   R => reset 	
			  );

u13  : FDR port map  (
			   Q => flop2(13),
			   C => clk,
			   D => flop1(13),
			   R => reset 	
			  );

u14  : FDR port map  (
			   Q => flop2n_14,
			   C => clk,
			   D => flop1(14),
			   R => reset 	
			  );

u15  : FDR port map  (
			   Q => flop2(15),
			   C => clk,
			   D => flop1(15),
			   R => reset 	
			  );

u16  : FDR port map  (
			   Q => flop2n_16,
			   C => clk,
			   D => flop1(16),
			   R => reset 	
			  );

u17  : FDR port map  (
			   Q => flop2(17),
			   C => clk,
			   D => flop1(17),
			   R => reset 	
			  );

u18  : FDR port map  (
			   Q => flop2n_18,
			   C => clk,
			   D => flop1(18),
			   R => reset 	
			  );

u19  : FDR port map  (
			   Q => flop2(19),
			   C => clk,
			   D => flop1(19),
			   R => reset 	
			  );

u20  : FDR port map  (
			   Q => flop2n_20,
			   C => clk,
			   D => flop1(20),
			   R => reset 	
			  );

u21  : FDR port map  (
			   Q => flop2(21),
			   C => clk,
			   D => flop1(21),
			   R => reset 	
			  );

u22  : FDR port map  (
			   Q => flop2n_22,
			   C => clk,
			   D => flop1(22),
			   R => reset 	
			  );

u23  : FDR port map  (
			   Q => flop2(23),
			   C => clk,
			   D => flop1(23),
			   R => reset 	
			  );

u24  : FDR port map  (
			   Q => flop2n_24,
			   C => clk,
			   D => flop1(24),
			   R => reset 	
			  );

u25  : FDR port map  (
			   Q => flop2(25),
			   C => clk,
			   D => flop1(25),
			   R => reset 	
			  );

u26  : FDR port map  (
			   Q => flop2n_26,
			   C => clk,
			   D => flop1(26),
			   R => reset 	
			  );

u27  : FDR port map  (
			   Q => flop2(27),
			   C => clk,
			   D => flop1(27),
			   R => reset 	
			  );

u28  : FDR port map  (
			   Q => flop2n_28,
			   C => clk,
			   D => flop1(28),
			   R => reset 	
			  );

u29  : FDR port map  (
			   Q => flop2(29),
			   C => clk,
			   D => flop1(29),
			   R => reset 	
			  );

u30  : FDR port map  (
			   Q => flop2n_30,
			   C => clk,
			   D => flop1(30),
			   R => reset 	
			  );

u31  : FDR port map  (
			   Q => flop2(31),
			   C => clk,
			   D => flop1(31),
			   R => reset 	
			  );			  
   

end arc_tap_dly;