cal_ctl.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity cal_ctl is
port (
	
	clk	    : in std_logic;
	reset	    : in std_logic;
	okToSelTap	 : in std_logic;
	flop2	    : in std_logic_vector(31 downto 0);
	tapForDqs_tb   : out std_logic_vector(4 downto 0);
	tapForDqs_rl   : out std_logic_vector(4 downto 0)
	);
end cal_ctl;
		
architecture arc_cal_ctl of cal_ctl is

attribute syn_keep : boolean;

signal  	cnt 		: std_logic_vector(5 downto 0);
signal   trans_oneDtct		: std_logic;
signal   trans_twoDtct		: std_logic;

signal  tapForDqs_val_rl   : std_logic_vector(4 downto 0);
signal  tapForDqs_val_tb   : std_logic_vector(4 downto 0);


signal 	phase_cnt       : std_logic_vector(4 downto 0);
signal  tapForDqs_val   : std_logic_vector(4 downto 0);
signal 	tap_dly_reg		: std_logic_vector(31 downto 0);	
signal  enb_trans_two_dtct : std_logic; 


constant tap1   : std_logic_vector(4 downto 0) := "01111";
constant tap2   : std_logic_vector(4 downto 0) := "10111";
constant tap3   : std_logic_vector(4 downto 0) := "11011";
constant tap4   : std_logic_vector(4 downto 0) := "11101";
constant tap5   : std_logic_vector(4 downto 0) := "11110";
constant tap6   : std_logic_vector(4 downto 0) := "11111";

constant defaultTap : std_logic_vector(4 downto 0) := "11101";

attribute syn_keep of trans_oneDtct : signal is true;
attribute syn_keep of trans_twoDtct : signal is true;
attribute syn_keep of tap_dly_reg : signal is true;
attribute syn_keep of enb_trans_two_dtct : signal is true;
attribute syn_keep of tapForDqs_val : signal is true;
--attribute syn_keep of tapForDqs : signal is true;
attribute syn_keep of phase_cnt : signal is true;
attribute syn_keep of tapForDqs_val_tb : signal is true;
attribute syn_keep of tapForDqs_val_rl : signal is true;


begin

tapForDqs_tb <= tapForDqs_val_tb;
tapForDqs_rl <= tapForDqs_val_rl;

process (clk)
begin
if (clk'event and clk ='1') then
   if (reset ='1') then
	enb_trans_two_dtct <= '0';
   elsif(phase_cnt >= "00011")	 then
	enb_trans_two_dtct <= '1';
   else
       enb_trans_two_dtct <= '0';		
   end if;
   end if;
 end process;

process (clk)
begin
 if (clk'event and clk= '1') then
     if (reset ='1')then
      	tap_dly_reg <= "00000000000000000000000000000000";  
     elsif(cnt(5) = '1') then
	 tap_dly_reg <= flop2;
     else
         tap_dly_reg <= tap_dly_reg;
     end if;
     end if;
end process;
   
process(clk)
begin

 if clk'event and clk = '1' then
  if (reset = '1' or  cnt(5) = '1')then
  	cnt <= "000000";
  else
  	cnt <= cnt + "000001";
  end if;
 end if;
end process;

process(clk)
  begin
   if clk'event and clk = '1' then
     if(reset = '1' or (cnt(5) = '1')) then
	phase_cnt <= "00000";

     else
      if (trans_oneDtct='1' and (( trans_twoDtct='0'))) then
        phase_cnt <= phase_cnt + "00001";
     else
        phase_cnt <= phase_cnt;
     end if;   
  end if;
  end if;
  end process;				

process (clk)
begin
   if clk'event and clk = '1' then
	if (reset = '1') then
		
		trans_oneDtct <= '0';
		trans_twoDtct <= '0';
	
		
	else 
	if(cnt(5) = '1') then
		trans_oneDtct <= '0';
		trans_twoDtct <= '0';
		
		
	elsif (cnt(4 downto 0) = "00000") then
		
            		if (flop2(0)='1' xor flop2(1)='1') then
			trans_oneDtct <= '1';
			trans_twoDtct <= '0';
  	        	end if;
	elsif ((cnt(4 downto 0) = "00001") and (trans_twoDtct = '0')) then
	 	if (flop2(1)='1' xor flop2(2)='1')  then
		   	
	  		if( trans_oneDtct = '1' and  enb_trans_two_dtct ='1' ) then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
            		
	elsif ((cnt(4 downto 0) = "00010") and (trans_twoDtct = '0')) then
	 	if (flop2(2)='1' xor flop2(3)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
            		
	elsif ((cnt(4 downto 0) = "00011") and (trans_twoDtct = '0')) then
	 	if (flop2(3)='1' xor flop2(4)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
            		
            		
	elsif ((cnt(4 downto 0) = "00100") and (trans_twoDtct = '0')) then
	 	if (flop2(4)='1' xor flop2(5)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
            		
	elsif ((cnt(4 downto 0) = "00101") and (trans_twoDtct = '0')) then
	 	if (flop2(5)='1' xor flop2(6)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
	elsif ((cnt(4 downto 0) = "00110") and (trans_twoDtct = '0')) then
	 	if (flop2(6)='1' xor flop2(7)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
	elsif ((cnt(4 downto 0) = "00111") and (trans_twoDtct = '0')) then
	 	if (flop2(7)='1' xor flop2(8)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
	elsif ((cnt(4 downto 0) = "01000") and (trans_twoDtct = '0')) then
	 	if (flop2(8)='1' xor flop2(9)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
	elsif ((cnt(4 downto 0) = "01001") and (trans_twoDtct = '0')) then
	 	if (flop2(9)='1' xor flop2(10)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
	elsif ((cnt(4 downto 0) = "01010") and (trans_twoDtct = '0')) then
	 	if (flop2(10)='1' xor flop2(11)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
	elsif ((cnt(4 downto 0) = "01011") and (trans_twoDtct = '0')) then
	 	if (flop2(11)='1' xor flop2(12)='1')  then
		   	
	  		if(trans_oneDtct = '1'  and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
	elsif ((cnt(4 downto 0) = "01100") and (trans_twoDtct = '0')) then
	 	if (flop2(12)='1' xor flop2(13)='1')  then
		   	
	  		if(trans_oneDtct = '1' and  enb_trans_two_dtct ='1') then
				trans_twoDtct <= '1';
			else
				trans_oneDtct <= '1';
			end if;
		else 
   			trans_oneDtct <= trans_oneDtct;    
			trans_twoDtct <= trans_twoDtct;    
     
            		end if;
	elsif ((cnt(4 downto 0) = "01101") and (trans_twoDtct = '0')) then