📄 tap_dly.vhd
字号:
--#############################################################################//
-- Internal dqs delay structure for ddr sdram controller //
--#############################################################################//
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
entity tap_dly is
port (
clk : in std_logic;
reset : in std_logic;
tapIn : in std_logic;
flop2 : out std_logic_vector(31 downto 0)
);
end tap_dly;
architecture arc_tap_dly of tap_dly is
-------------------------------------------------------------------------------------------------------------------------------
attribute syn_keep : boolean;
-------------------------------------------------------------------------------------------------------------------------------
component LUT4
generic(
INIT : bit_vector(15 downto 0) := x"0000" );
port(
O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC
);
end component;
component FDR
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
R : in STD_LOGIC
);
end component;
signal tap : std_logic_vector(31 downto 0);
signal flop1 : std_logic_vector(31 downto 0);
signal high : std_logic;
----------------------------------------------------------------------------------------------------------------------
attribute syn_keep of flop1 : signal is true;
attribute syn_keep of tap : signal is true;
----------------------------------------------------------------------------------------------------------------------
begin
high <= '1';
l0 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tapIn,
O => tap(0)
);
l1 : LUT4 generic map (INIT => x"4000")
port map ( I0 => tap(0),
I1 => high,
I2 => high,
I3 => high,
O => tap(1)
);
l2 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(1),
O => tap(2)
);
l3 : LUT4 generic map (INIT => x"0800")
port map ( I0 => high,
I1 => high,
I2 => tap(2),
I3 => high,
O => tap(3)
);
l4 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(3),
O => tap(4)
);
l5 : LUT4 generic map (INIT => x"0800")
port map ( I0 => high,
I1 => high,
I2 => tap(4),
I3 => high,
O => tap(5)
);
l6 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(5),
O => tap(6)
);
l7 : LUT4 generic map (INIT => x"4000")
port map ( I0 => tap(6),
I1 => high,
I2 => high,
I3 => high,
O => tap(7)
);
l8 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(7),
O => tap(8)
);
l9 : LUT4 generic map (INIT => x"4000")
port map ( I0 => tap(8),
I1 => high,
I2 => high,
I3 => high,
O => tap(9)
);
l10 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(9),
O => tap(10)
);
l11 : LUT4 generic map (INIT => x"0800")
port map ( I0 => high,
I1 => high,
I2 => tap(10),
I3 => high,
O => tap(11)
);
l12 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(11),
O => tap(12)
);
l13 : LUT4 generic map (INIT => x"0800")
port map ( I0 => high,
I1 => high,
I2 => tap(12),
I3 => high,
O => tap(13)
);
l14 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(13),
O => tap(14)
);
l15 : LUT4 generic map (INIT => x"4000")
port map ( I0 => tap(14),
I1 => high,
I2 => high,
I3 => high,
O => tap(15)
);
l16 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(15),
O => tap(16)
);
l17 : LUT4 generic map (INIT => x"0800")
port map ( I0 => high,
I1 => high,
I2 => tap(16),
I3 => high,
O => tap(17)
);
l18 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(17),
O => tap(18)
);
l19 : LUT4 generic map (INIT => x"0800")
port map ( I0 => high,
I1 => high,
I2 => tap(18),
I3 => high,
O => tap(19)
);
l20 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(19),
O => tap(20)
);
l21 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(20),
O => tap(21)
);
l22 : LUT4 generic map (INIT => x"4000")
port map ( I0 => tap(21),
I1 => high,
I2 => high,
I3 => high,
O => tap(22)
);
l23 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(22),
O => tap(23)
);
l24 : LUT4 generic map (INIT => x"0800")
port map ( I0 => high,
I1 => high,
I2 => tap(23),
I3 => high,
O => tap(24)
);
l25 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(24),
O => tap(25)
);
l26 : LUT4 generic map (INIT => x"0800")
port map ( I0 => high,
I1 => high,
I2 => tap(25),
I3 => high,
O => tap(26)
);
l27 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(26),
O => tap(27)
);
l28 : LUT4 generic map (INIT => x"4000")
port map ( I0 => tap(27),
I1 => high,
I2 => high,
I3 => high,
O => tap(28)
);
l29 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(28),
O => tap(29)
);
l30 : LUT4 generic map (INIT => x"4000")
port map ( I0 => tap(29),
I1 => high,
I2 => high,
I3 => high,
O => tap(30)
);
l31 : LUT4 generic map (INIT => x"0080")
port map ( I0 => high,
I1 => high,
I2 => high,
I3 => tap(30),
O => tap(31)
);
r0 : FDR port map (
Q => flop1(0),
C => clk,
D => tap(0),
R => reset
);
r1 : FDR port map (
Q => flop1(1),
C => clk,
D => tap(1),
R => reset
);
r2 : FDR port map (
Q => flop1(2),
C => clk,
D => tap(2),
R => reset
);
r3 : FDR port map (
Q => flop1(3),
C => clk,
D => tap(3),
R => reset
);
r4 : FDR port map (
Q => flop1(4),
C => clk,
D => tap(4),
R => reset
);
r5 : FDR port map (
Q => flop1(5),
C => clk,
D => tap(5),
R => reset
);
r6 : FDR port map (
Q => flop1(6),
C => clk,
D => tap(6),
R => reset
);
r7 : FDR port map (
Q => flop1(7),
C => clk,
D => tap(7),
R => reset
);
r8 : FDR port map (
Q => flop1(8),
C => clk,
D => tap(8),
R => reset
);
r9 : FDR port map (
Q => flop1(9),
C => clk,
D => tap(9),
R => reset
);
r10 : FDR port map (
Q => flop1(10),
C => clk,
D => tap(10),
R => reset
);
r11 : FDR port map (
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -