rd_gray_cntr.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

-- fifo_rd_addr gray counter with synchronous reset

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--



ENTITY  rd_gray_cntr IS
	port (
			clk 				: 	in std_logic;         
			reset				:	in std_logic;
			cnt_en			:	in std_logic;         
			rgc_gcnt			:	out	std_logic_vector(3 downto 0)
		  );
END rd_gray_cntr;

ARCHITECTURE rd_gray_cntr OF rd_gray_cntr IS

component FDRE
    port(
      Q                              :	out   STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
	  	R													 :	in    STD_ULOGIC
      );
end component;
 
-- gray encoded signals

signal  gc_int :  std_logic_vector(3 downto 0);
signal  d_in   :  std_logic_vector(3 downto 0);  

BEGIN

    rgc_gcnt <= gc_int(3 downto 0);

process(gc_int)
	begin
		case gc_int is 
			when "0000" => d_in <= "0001";  --0 > 1
			when "0001" => d_in <= "0011";  --1 > 3
			when "0010" => d_in <= "0110";  --2 > 6
			when "0011" => d_in <= "0010";  --3 > 2
			when "0100" => d_in <= "1100";  --4 > c
			when "0101" => d_in <= "0100";  --5 > 4
			when "0110" => d_in <= "0111";  --6 > 7
			when "0111" => d_in <= "0101";  --7 > 5
			when "1000" => d_in <= "0000";  --8 > 0
 			when "1001" => d_in <= "1000";  --9 > 8
			when "1010" => d_in <= "1011";  --10 > b
			when "1011" => d_in <= "1001";  --11 > 9
			when "1100" => d_in <= "1101";  --12 > d
			when "1101" => d_in <= "1111";  --13 > f
			when "1110" => d_in <= "1010";  --14 > a
			when "1111" => d_in <= "1110";  --15 > e
			when others => d_in <= "0001";  --0 > 1
		end case;					
end process;

bit0 : FDRE port map (
                      Q   => gc_int(0),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d_in(0),
			    						 R   => reset
                     );

bit1 : FDRE port map (
                      Q   => gc_int(1),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d_in(1),
			    						R   => reset
                     );

bit2 : FDRE port map (
                      Q   => gc_int(2),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d_in(2),
			 					   R   => reset
                     );

bit3 : FDRE port map (
                      Q   => gc_int(3),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d_in(3),
							    R   => reset
                     );


END rd_gray_cntr;