mybufg.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity myBUFG is
port (I : in std_logic;
      O : out std_logic);
end myBUFG;

architecture mybufg_arch of mybufg is

attribute syn_hier : string;
attribute syn_hier of mybufg_arch: architecture is "hard";

component BUFG
port (I : in std_logic;
      O : out std_logic);
end component;

begin

u1 : BUFG port map (I  => I,
								 O  => O);


end mybufg_arch;