📄 cal_ctl.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
entity cal_ctl is
port (
clk : in std_logic;
reset : in std_logic;
okToSelTap : in std_logic;
flop2 : in std_logic_vector(31 downto 0);
tapForDqs_tb : out std_logic_vector(4 downto 0);
tapForDqs_rl : out std_logic_vector(4 downto 0)
);
end cal_ctl;
architecture arc_cal_ctl of cal_ctl is
attribute syn_keep : boolean;
signal cnt : std_logic_vector(5 downto 0);
signal trans_oneDtct : std_logic;
signal trans_twoDtct : std_logic;
signal phase_cnt : std_logic_vector(4 downto 0);
signal tapForDqs_val_rl : std_logic_vector(4 downto 0);
signal tapForDqs_val_tb : std_logic_vector(4 downto 0);
signal tap_dly_reg : std_logic_vector(31 downto 0);
signal enb_trans_two_dtct : std_logic;
constant tap1 : std_logic_vector(4 downto 0) := "01111";
constant tap2 : std_logic_vector(4 downto 0) := "10111";
constant tap3 : std_logic_vector(4 downto 0) := "11011";
constant tap4 : std_logic_vector(4 downto 0) := "11101";
constant tap5 : std_logic_vector(4 downto 0) := "11110";
constant tap6 : std_logic_vector(4 downto 0) := "11111";
constant defaultTap : std_logic_vector(4 downto 0) := "11101";
attribute syn_keep of trans_oneDtct : signal is true;
attribute syn_keep of trans_twoDtct : signal is true;
attribute syn_keep of tap_dly_reg : signal is true;
attribute syn_keep of enb_trans_two_dtct : signal is true;
attribute syn_keep of tapForDqs_val_tb : signal is true;
attribute syn_keep of tapForDqs_val_rl : signal is true;
attribute syn_keep of tapForDqs_tb : signal is true;
attribute syn_keep of tapForDqs_rl : signal is true;
attribute syn_keep of phase_cnt : signal is true;
signal flop_0_1 : std_logic;
signal flop_1_2 : std_logic;
signal flop_2_3 : std_logic;
signal flop_3_4 : std_logic;
signal flop_4_5 : std_logic;
signal flop_5_6 : std_logic;
signal flop_6_7 : std_logic;
signal flop_7_8 : std_logic;
signal flop_8_9 : std_logic;
signal flop_9_10 : std_logic;
signal flop_10_11 : std_logic;
signal flop_11_12 : std_logic;
signal flop_12_13 : std_logic;
signal flop_13_14 : std_logic;
signal flop_14_15 : std_logic;
signal flop_15_16 : std_logic;
signal flop_16_17 : std_logic;
signal flop_17_18 : std_logic;
signal flop_18_19 : std_logic;
signal flop_19_20 : std_logic;
signal flop_20_21 : std_logic;
signal flop_21_22 : std_logic;
signal flop_22_23 : std_logic;
signal flop_23_24 : std_logic;
signal flop_24_25 : std_logic;
signal flop_25_26 : std_logic;
signal flop_26_27 : std_logic;
signal flop_27_28 : std_logic;
signal flop_28_29 : std_logic;
signal flop_29_30 : std_logic;
signal flop_30_31 : std_logic;
signal flop_31_32 : std_logic;
attribute syn_keep of flop_0_1 : signal is true;
attribute syn_keep of flop_1_2 : signal is true;
attribute syn_keep of flop_2_3 : signal is true;
attribute syn_keep of flop_3_4 : signal is true;
attribute syn_keep of flop_4_5 : signal is true;
attribute syn_keep of flop_5_6 : signal is true;
attribute syn_keep of flop_6_7 : signal is true;
attribute syn_keep of flop_7_8 : signal is true;
attribute syn_keep of flop_8_9 : signal is true;
attribute syn_keep of flop_9_10 : signal is true;
attribute syn_keep of flop_10_11 : signal is true;
attribute syn_keep of flop_11_12 : signal is true;
attribute syn_keep of flop_12_13 : signal is true;
attribute syn_keep of flop_13_14 : signal is true;
attribute syn_keep of flop_14_15 : signal is true;
attribute syn_keep of flop_15_16 : signal is true;
attribute syn_keep of flop_16_17 : signal is true;
attribute syn_keep of flop_17_18 : signal is true;
attribute syn_keep of flop_18_19 : signal is true;
attribute syn_keep of flop_19_20 : signal is true;
attribute syn_keep of flop_20_21 : signal is true;
attribute syn_keep of flop_21_22 : signal is true;
attribute syn_keep of flop_22_23 : signal is true;
attribute syn_keep of flop_23_24 : signal is true;
attribute syn_keep of flop_24_25 : signal is true;
attribute syn_keep of flop_25_26 : signal is true;
attribute syn_keep of flop_26_27 : signal is true;
attribute syn_keep of flop_27_28 : signal is true;
attribute syn_keep of flop_28_29 : signal is true;
attribute syn_keep of flop_29_30 : signal is true;
attribute syn_keep of flop_30_31 : signal is true;
begin
flop_0_1 <= not(flop2(0) xor flop2(1));
flop_1_2 <= not(flop2(1) xor flop2(2));
flop_2_3 <= not(flop2(2) xor flop2(3));
flop_3_4 <= not(flop2(3) xor flop2(4));
flop_4_5 <= not(flop2(4) xor flop2(5));
flop_5_6 <= not(flop2(5) xor flop2(6));
flop_6_7 <= not(flop2(6) xor flop2(7));
flop_7_8 <= not(flop2(7) xor flop2(8));
flop_8_9 <= not(flop2(8) xor flop2(9));
flop_9_10 <= not(flop2(9) xor flop2(10));
flop_10_11 <= not(flop2(10) xor flop2(11));
flop_11_12 <= not(flop2(11) xor flop2(12));
flop_12_13 <= not(flop2(12) xor flop2(13));
flop_13_14 <= not(flop2(13) xor flop2(14));
flop_14_15 <= not(flop2(14) xor flop2(15));
flop_15_16 <= not(flop2(15) xor flop2(16));
flop_16_17 <= not(flop2(16) xor flop2(17));
flop_17_18 <= not(flop2(17) xor flop2(18));
flop_18_19 <= not(flop2(18) xor flop2(19));
flop_19_20 <= not(flop2(19) xor flop2(20));
flop_20_21 <= not(flop2(20) xor flop2(21));
flop_21_22 <= not(flop2(21) xor flop2(22));
flop_22_23 <= not(flop2(22) xor flop2(23));
flop_23_24 <= not(flop2(23) xor flop2(24));
flop_24_25 <= not(flop2(24) xor flop2(25));
flop_25_26 <= not(flop2(25) xor flop2(26));
flop_26_27 <= not(flop2(26) xor flop2(27));
flop_27_28 <= not(flop2(27) xor flop2(28));
flop_28_29 <= not(flop2(28) xor flop2(29));
flop_29_30 <= not(flop2(29) xor flop2(30));
flop_30_31 <= not(flop2(30) xor flop2(31));
tapForDqs_tb <= tapForDqs_val_tb;
tapForDqs_rl <= tapForDqs_val_rl;
process (clk)
begin
if (clk'event and clk ='1') then
if (reset ='1') then
enb_trans_two_dtct <= '0';
elsif(phase_cnt >= "00011") then
enb_trans_two_dtct <= '1';
else
enb_trans_two_dtct <= '0';
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk= '1') then
if (reset ='1')then
tap_dly_reg <= "00000000000000000000000000000000";
elsif(cnt(5) = '1') then
tap_dly_reg <= flop2;
else
tap_dly_reg <= tap_dly_reg;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if (reset = '1' or cnt(5) = '1')then
cnt <= "000000";
else
cnt <= cnt + "000001";
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if(reset = '1' or (cnt(5) = '1')) then
phase_cnt <= "00000";
else
if (trans_oneDtct='1' and (( trans_twoDtct='0'))) then
phase_cnt <= phase_cnt + "00001";
else
phase_cnt <= phase_cnt;
end if;
end if;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
if (reset = '1') then
trans_oneDtct <= '0';
trans_twoDtct <= '0';
else
if(cnt(5) = '1') then
trans_oneDtct <= '0';
trans_twoDtct <= '0';
elsif (cnt(4 downto 0) = "00000") then
if (flop_0_1 = '1' ) then
trans_oneDtct <= '1';
trans_twoDtct <= '0';
end if;
elsif ((cnt(4 downto 0) = "00001") and (trans_twoDtct = '0')) then
if (flop_1_2 = '1' ) then
if( trans_oneDtct = '1' and enb_trans_two_dtct ='1' ) then
trans_twoDtct <= '1';
else
trans_oneDtct <= '1';
end if;
else
trans_oneDtct <= trans_oneDtct;
trans_twoDtct <= trans_twoDtct;
end if;
elsif ((cnt(4 downto 0) = "00010") and (trans_twoDtct = '0')) then
if (flop_2_3 = '1' ) then
if(trans_oneDtct = '1' and enb_trans_two_dtct ='1') then
trans_twoDtct <= '1';
else
trans_oneDtct <= '1';
end if;
else
trans_oneDtct <= trans_oneDtct;
trans_twoDtct <= trans_twoDtct;
end if;
elsif ((cnt(4 downto 0) = "00011") and (trans_twoDtct = '0')) then
if (flop_3_4 = '1' ) then
if(trans_oneDtct = '1' and enb_trans_two_dtct ='1') then
trans_twoDtct <= '1';
else
trans_oneDtct <= '1';
end if;
else
trans_oneDtct <= trans_oneDtct;
trans_twoDtct <= trans_twoDtct;
end if;
elsif ((cnt(4 downto 0) = "00100") and (trans_twoDtct = '0')) then
if (flop_4_5 = '1' ) then
if(trans_oneDtct = '1' and enb_trans_two_dtct ='1') then
trans_twoDtct <= '1';
else
trans_oneDtct <= '1';
end if;
else
trans_oneDtct <= trans_oneDtct;
trans_twoDtct <= trans_twoDtct;
end if;
elsif ((cnt(4 downto 0) = "00101") and (trans_twoDtct = '0')) then
if (flop_5_6 = '1' ) then
if(trans_oneDtct = '1' and enb_trans_two_dtct ='1') then
trans_twoDtct <= '1';
else
trans_oneDtct <= '1';
end if;
else
trans_oneDtct <= trans_oneDtct;
trans_twoDtct <= trans_twoDtct;
end if;
elsif ((cnt(4 downto 0) = "00110") and (trans_twoDtct = '0')) then
if (flop_6_7 = '1' ) then
if(trans_oneDtct = '1' and enb_trans_two_dtct ='1') then
trans_twoDtct <= '1';
else
trans_oneDtct <= '1';
end if;
else
trans_oneDtct <= trans_oneDtct;
trans_twoDtct <= trans_twoDtct;
end if;
elsif ((cnt(4 downto 0) = "00111") and (trans_twoDtct = '0')) then
if (flop_7_8 = '1' ) then
if(trans_oneDtct = '1' and enb_trans_two_dtct ='1') then
trans_twoDtct <= '1';
else
trans_oneDtct <= '1';
end if;
else
trans_oneDtct <= trans_oneDtct;
trans_twoDtct <= trans_twoDtct;
end if;
elsif ((cnt(4 downto 0) = "01000") and (trans_twoDtct = '0')) then
if (flop_8_9 = '1' ) then
if(trans_oneDtct = '1' and enb_trans_two_dtct ='1') then
trans_twoDtct <= '1';
else
trans_oneDtct <= '1';
end if;
else
trans_oneDtct <= trans_oneDtct;
trans_twoDtct <= trans_twoDtct;
end if;
elsif ((cnt(4 downto 0) = "01001") and (trans_twoDtct = '0')) then
if (flop_9_10 = '1' ) then
if(trans_oneDtct = '1' and enb_trans_two_dtct ='1') then
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