fifo_0_wr_en.vhd

来自「XILINX memory interface generator. XILI」· VHDL 代码 · 共 78 行

--  fifo_wr_en is derived  by ORing -
--  "rst_dqs_div" , delayed rst_dqs_div with negedge of the ddr_dqs 

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--



ENTITY fifo_0_wr_en IS
-- Declarations
port (
		clk		: 	in std_logic; 
     		reset		:	in std_logic; 
		din		:	in std_logic;
		rst_dqs_delay_n : 			out std_logic;
		dout		:	out std_logic
	  );
END fifo_0_wr_en ;

-- hds interface_end
ARCHITECTURE fifo_0_wr_en OF fifo_0_wr_en IS

component FDCE
    port(
      Q                              :	out   STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      CE                             :	in    STD_ULOGIC;
      CLR                            :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC     
      );
end component;

--- Added By Praveen 17th March

component LUT4
   generic(
      INIT                           :  bit_vector(15 downto 0) := x"0000" );
   port(
      O                              :	out   STD_ULOGIC;
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC
      );
end component;		  


attribute syn_keep : boolean;  -- Using Syn_Keep Derictive

signal	din_delay	:	STD_ULOGIC;
signal  TIE_HIGH    : 	STD_ULOGIC;
 

BEGIN

	rst_dqs_delay_n <= not din_delay;
	dout <= din or din_delay;
	TIE_HIGH <= '1';


delay_ff : FDCE port map (
                      Q   => din_delay,
                      C   => clk,
                      CE  => TIE_HIGH,
                      CLR => reset,
                      D   => din
                     );

END fifo_0_wr_en;