cal_top.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
--library synplify; 
--use synplify.attributes.all; 



entity cal_top is
port(
     clk         : in std_logic;
     clk0dcmlock : in std_logic;
     reset       : in std_logic;
     okToSelTap  : in std_logic;
     tapForDqs_tb   : out std_logic_vector( 4 downto 0);
     tapForDqs_rl   : out std_logic_vector( 4 downto 0)
     );
end cal_top;

architecture arc_cal_top of cal_top is

component cal_ctl 
port (
	
	clk	    : in std_logic;
	reset	    : in std_logic;
	okToSelTap	 : in std_logic;
	flop2	    : in std_logic_vector(31 downto 0);
	tapForDqs_tb   : out std_logic_vector(4 downto 0);
	tapForDqs_rl   : out std_logic_vector(4 downto 0)
	);
end component;


component tap_dly
port (
      clk 	      	    : in std_logic;
      reset 	    	    : in std_logic;
      tapIn 	    	    : in std_logic;
      flop2 	    	    : out std_logic_vector(31 downto 0)
      );
 end component;     
 

signal fpga_rst 		    : std_logic;
signal flop2_val 		   : std_logic_vector(31 downto 0); 

begin

process (clk)
begin
	if clk'event and clk = '1' then
    		fpga_rst <= not (reset and  clk0dcmlock);
  	end if;
end process;

cal_ctl0: cal_ctl port map(
     				
     			clk            		 => clk,	
     			reset             => fpga_rst,
     			okToSelTap        => okToSelTap,
     			flop2	          => flop2_val,	
     			tapForDqs_tb         => tapForDqs_tb,
     			tapForDqs_rl         => tapForDqs_rl
     			);


tap_dly0: tap_dly port map (
      			clk 	      	    => clk,
      			reset 	    	    => fpga_rst,
      			tapIn 	    	    => clk,
      			flop2 	    	    => flop2_val
      			);
 
end arc_cal_top;