data_read.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*********************************************************************
-- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins

-- In the current DATA PATH logic DATA CAPTURE part was modified.
-- The below changes were made to reduce the resources in 
-- the data capture

-- in the current architecture data ( dq ) from ddr memory 
-- directly stored into the FIFO's.

-- Architectural changes :

-- Used only TWO FIFOs ( instead of FOUR FIFOs ) 
-- Used Single col ( col0 ) dqs_delayed_col signals
-- Used Gray Counters for write and read pointers of the FIFOs 

-- fbit stage is removed from ddr1_dqbit module ( in the data capture )
-- dq_clk stage was removed 
-- dqs_clk_div logic was removed
-- ddr1_transfer_done logic was removed 
-- data valid signals registering in clk90 domain was removed

-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic  
-- write enable for the FIFOs derived from rst_dqs_div signal


-- Code revised by 	: Narayana Murty.
-- Date 			      : Nov 18, 2003. 

--*********************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--

entity data_read is
port(
     clk                : in std_logic;
     clk90              : in std_logic;
     reset90_r          : in std_logic;
     reset270_r         : in std_logic;
     ddr_dq_in          : in std_logic_vector(127 downto 0);   
     read_valid_data_1  : in std_logic;    
     fifo_00_wr_en	: in std_logic;
     fifo_10_wr_en	: in std_logic;
     fifo_20_wr_en	: in std_logic;
     fifo_30_wr_en	: in std_logic;
     fifo_40_wr_en	: in std_logic;
     fifo_50_wr_en	: in std_logic;
     fifo_60_wr_en	: in std_logic;
     fifo_70_wr_en	: in std_logic;
     fifo_80_wr_en	: in std_logic;
     fifo_90_wr_en	: in std_logic;
     fifo_100_wr_en	: in std_logic;
     fifo_110_wr_en	: in std_logic;
     fifo_120_wr_en	: in std_logic;
     fifo_130_wr_en	: in std_logic;
     fifo_140_wr_en	: in std_logic;
     fifo_150_wr_en	: in std_logic;
     fifo_01_wr_en	: in std_logic;
     fifo_11_wr_en	: in std_logic;
     fifo_21_wr_en	: in std_logic;
     fifo_31_wr_en	: in std_logic;
     fifo_41_wr_en	: in std_logic;
     fifo_51_wr_en	: in std_logic;
     fifo_61_wr_en	: in std_logic;
     fifo_71_wr_en	: in std_logic;
     fifo_81_wr_en	: in std_logic;	
     fifo_91_wr_en	: in std_logic;
     fifo_101_wr_en	: in std_logic;
     fifo_111_wr_en	: in std_logic;
     fifo_121_wr_en	: in std_logic;
     fifo_131_wr_en	: in std_logic;
     fifo_141_wr_en	: in std_logic;
     fifo_151_wr_en	: in std_logic;	
     fifo_00_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_01_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_10_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_11_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_20_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_21_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_30_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_31_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_40_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_41_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_50_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_51_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_60_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_61_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_70_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_71_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_80_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_81_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_90_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_91_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_100_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_101_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_110_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_111_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_120_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_121_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_130_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_131_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_140_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_141_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_150_wr_addr   : in std_logic_vector(3 downto 0);
     fifo_151_wr_addr   : in std_logic_vector(3 downto 0);		
     dqs0_delayed_col1  : in std_logic;
     dqs1_delayed_col1  : in std_logic;
     dqs2_delayed_col1  : in std_logic;
     dqs3_delayed_col1  : in std_logic;
     dqs4_delayed_col1  : in std_logic;
     dqs5_delayed_col1  : in std_logic;
     dqs6_delayed_col1  : in std_logic;
     dqs7_delayed_col1  : in std_logic;
     dqs8_delayed_col1  : in std_logic;
     dqs9_delayed_col1  : in std_logic;
     dqs10_delayed_col1 : in std_logic;
     dqs11_delayed_col1 : in std_logic;
     dqs12_delayed_col1 : in std_logic;
     dqs13_delayed_col1 : in std_logic;
     dqs14_delayed_col1 : in std_logic;
     dqs15_delayed_col1 : in std_logic;     
     dqs0_delayed_col0_n: in std_logic;
     dqs1_delayed_col0_n: in std_logic;
     dqs2_delayed_col0_n: in std_logic;
     dqs3_delayed_col0_n: in std_logic;
     dqs4_delayed_col0_n: in std_logic;
     dqs5_delayed_col0_n: in std_logic;
     dqs6_delayed_col0_n: in std_logic;
     dqs7_delayed_col0_n: in std_logic;
     dqs8_delayed_col0_n: in std_logic;   
     dqs9_delayed_col0_n: in std_logic;
     dqs10_delayed_col0_n: in std_logic;
     dqs11_delayed_col0_n: in std_logic;
     dqs12_delayed_col0_n: in std_logic;
     dqs13_delayed_col0_n: in std_logic;
     dqs14_delayed_col0_n: in std_logic;
     dqs15_delayed_col0_n: in std_logic;  
     user_output_data   : out std_logic_vector(255 downto 0);
     fifo0_rd_addr      : in std_logic_vector(3 downto 0);
     fifo1_rd_addr      : in std_logic_vector(3 downto 0)     

     );
end data_read;


architecture arc_data_read of data_read is

attribute syn_keep : boolean;  -- Using Syn_Keep Derictive




component FD port(
      Q        : out STD_LOGIC;
      C        : in STD_LOGIC;
      D        : in STD_LOGIC
      );
end component;

-- 16x1 Dual Port RAM Component Instansiated 

component RAM16X1D
  port (D     : in std_logic;
        WE    : in std_logic;
        WCLK  : in std_logic;
        A0    : in std_logic;
        A1    : in std_logic;
        A2    : in std_logic;
        A3    : in std_logic;
        DPRA0 : in std_logic;
        DPRA1 : in std_logic;
        DPRA2 : in std_logic;
        DPRA3 : in std_logic;
 		  SPO   : out std_logic;
        DPO   : out std_logic);

end component;




signal fifo_00_data_out       : std_logic_vector(7 downto 0);
signal fifo_01_data_out       : std_logic_vector(7 downto 0);
signal fifo_10_data_out       : std_logic_vector(7 downto 0);
signal fifo_11_data_out       : std_logic_vector(7 downto 0);
signal fifo_20_data_out       : std_logic_vector(7 downto 0);
signal fifo_21_data_out       : std_logic_vector(7 downto 0);
signal fifo_30_data_out       : std_logic_vector(7 downto 0);
signal fifo_31_data_out       : std_logic_vector(7 downto 0);
signal fifo_40_data_out       : std_logic_vector(7 downto 0);
signal fifo_41_data_out       : std_logic_vector(7 downto 0);
signal fifo_50_data_out       : std_logic_vector(7 downto 0);
signal fifo_51_data_out       : std_logic_vector(7 downto 0);
signal fifo_60_data_out       : std_logic_vector(7 downto 0);
signal fifo_61_data_out       : std_logic_vector(7 downto 0);
signal fifo_70_data_out       : std_logic_vector(7 downto 0);
signal fifo_71_data_out       : std_logic_vector(7 downto 0);
signal fifo_80_data_out       : std_logic_vector(7 downto 0);
signal fifo_81_data_out       : std_logic_vector(7 downto 0);
signal fifo_90_data_out       : std_logic_vector(7 downto 0);
signal fifo_91_data_out       : std_logic_vector(7 downto 0);
signal fifo_100_data_out       : std_logic_vector(7 downto 0);
signal fifo_101_data_out       : std_logic_vector(7 downto 0);
signal fifo_110_data_out       : std_logic_vector(7 downto 0);
signal fifo_111_data_out       : std_logic_vector(7 downto 0);
signal fifo_120_data_out       : std_logic_vector(7 downto 0);
signal fifo_121_data_out       : std_logic_vector(7 downto 0);
signal fifo_130_data_out       : std_logic_vector(7 downto 0);
signal fifo_131_data_out       : std_logic_vector(7 downto 0);
signal fifo_140_data_out       : std_logic_vector(7 downto 0);
signal fifo_141_data_out       : std_logic_vector(7 downto 0);
signal fifo_150_data_out       : std_logic_vector(7 downto 0);
signal fifo_151_data_out       : std_logic_vector(7 downto 0);

signal first_sdr_data         : std_logic_vector(255 downto 0);

begin

user_output_data    <= first_sdr_data;



process(clk90)
begin
if clk90'event and clk90 = '1' then
 if reset90_r = '1' then
    first_sdr_data   <= (others => '0');  
 else
             if (read_valid_data_1 = '1') then    
               		first_sdr_data  <= fifo_150_data_out & fifo_140_data_out & 
							fifo_130_data_out & fifo_120_data_out & 
							fifo_110_data_out & fifo_100_data_out & 
							fifo_90_data_out & fifo_80_data_out & 
							fifo_70_data_out & fifo_60_data_out & 
							fifo_50_data_out & fifo_40_data_out & 
							fifo_30_data_out & fifo_20_data_out & 
							fifo_10_data_out & fifo_00_data_out & 
							fifo_151_data_out & fifo_141_data_out & 
							fifo_131_data_out & fifo_121_data_out & 
							fifo_111_data_out & fifo_101_data_out & 
							fifo_91_data_out & fifo_81_data_out & 
							fifo_71_data_out & fifo_61_data_out & 
							fifo_51_data_out & fifo_41_data_out & 
							fifo_31_data_out & fifo_21_data_out & 
							fifo_11_data_out & fifo_01_data_out;
             else
               first_sdr_data  <= first_sdr_data;               
             end if;              
end if;                                                    
end if;                                                    
end process;     
   

--*************************************************************************************************************************
-- Dual Port RAM 16x1 instantiations (fifo0 -- Positive edge, fifo1 -- Trailing edge) 
--*************************************************************************************************************************

--- Byte0 instantiation

fifo0_bit0 : RAM16X1D               
port map (DPO    => fifo_00_data_out(0),          
          A0     => fifo_00_wr_addr(0),          
          A1     => fifo_00_wr_addr(1),
          A2     => fifo_00_wr_addr(2),
          A3     => fifo_00_wr_addr(3),
          D      => ddr_dq_in(0),      
          DPRA0  => fifo0_rd_addr(0),
          DPRA1  => fifo0_rd_addr(1),
          DPRA2  => fifo0_rd_addr(2),
          DPRA3  => fifo0_rd_addr(3),
          WCLK   => dqs0_delayed_col1,          
          WE     => fifo_00_wr_en );                       

fifo1_bit0 : RAM16X1D               
port map (DPO    => fifo_01_data_out(0),          
          A0     => fifo_01_wr_addr(0),          
          A1     => fifo_01_wr_addr(1),
          A2     => fifo_01_wr_addr(2),
          A3     => fifo_01_wr_addr(3),
          D      => ddr_dq_in(0),      
          DPRA0  => fifo1_rd_addr(0),
          DPRA1  => fifo1_rd_addr(1),
          DPRA2  => fifo1_rd_addr(2),
          DPRA3  => fifo1_rd_addr(3),
          WCLK   => dqs0_delayed_col0_n,          
          WE     => fifo_01_wr_en ); 
                      
fifo0_bit1 : RAM16X1D               
port map (DPO    => fifo_00_data_out(1),          
          A0     => fifo_00_wr_addr(0),          
          A1     => fifo_00_wr_addr(1),
          A2     => fifo_00_wr_addr(2),
          A3     => fifo_00_wr_addr(3),
          D      => ddr_dq_in(1),      
          DPRA0  => fifo0_rd_addr(0),
          DPRA1  => fifo0_rd_addr(1),
          DPRA2  => fifo0_rd_addr(2),
          DPRA3  => fifo0_rd_addr(3),
          WCLK   => dqs0_delayed_col1,          
          WE     => fifo_00_wr_en );                       

fifo1_bit1 : RAM16X1D               
port map (DPO    => fifo_01_data_out(1),          
          A0     => fifo_01_wr_addr(0),          
          A1     => fifo_01_wr_addr(1),
          A2     => fifo_01_wr_addr(2),
          A3     => fifo_01_wr_addr(3),
          D      => ddr_dq_in(1),      
          DPRA0  => fifo1_rd_addr(0),
          DPRA1  => fifo1_rd_addr(1),
          DPRA2  => fifo1_rd_addr(2),
          DPRA3  => fifo1_rd_addr(3),
          WCLK   => dqs0_delayed_col0_n,          
          WE     => fifo_01_wr_en );