📄 data_read_controller.vhd
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-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay10_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in10,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(10)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay11_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in11,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(11)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay11_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in11,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(11)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay12_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in12,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(12)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay12_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in12,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(12)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay13_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in13,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(13)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay13_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in13,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(13)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay14_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in14,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(14)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay14_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in14,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(14)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay15_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in15,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(15)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay15_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in15,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(15)
);
-------------------------------------------------------------------------------------------------
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-- FIFO Write enable signal generation
-- FIFO Write enable signal generation
fifo_00_wr_en_inst: fifo_0_wr_en port map (
clk => dqs0_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div1,
rst_dqs_delay_n => rst_dqs_delay_0_n,
dout => fifo_00_wr_en
);
fifo_01_wr_en_inst: fifo_1_wr_en port map (
clk => dqs0_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_0_n,
reset => reset_r,
din => rst_dqs_div1,
dout => fifo_01_wr_en
);
fifo_10_wr_en_inst: fifo_0_wr_en port map (
clk => dqs1_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div1,
rst_dqs_delay_n => rst_dqs_delay_1_n,
dout => fifo_10_wr_en
);
fifo_11_wr_en_inst: fifo_1_wr_en port map (
clk => dqs1_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_1_n,
reset => reset_r,
din => rst_dqs_div1,
dout => fifo_11_wr_en
);
fifo_20_wr_en_inst: fifo_0_wr_en port map (
clk => dqs2_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div1,
rst_dqs_delay_n => rst_dqs_delay_2_n,
dout => fifo_20_wr_en
);
fifo_21_wr_en_inst: fifo_1_wr_en port map (
clk => dqs2_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_2_n,
reset => reset_r,
din => rst_dqs_div1,
dout => fifo_21_wr_en
);
fifo_30_wr_en_inst: fifo_0_wr_en port map (
clk => dqs3_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div1,
rst_dqs_delay_n => rst_dqs_delay_3_n,
dout => fifo_30_wr_en
);
fifo_31_wr_en_inst: fifo_1_wr_en port map (
clk => dqs3_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_3_n,
reset => reset_r,
din => rst_dqs_div1,
dout => fifo_31_wr_en
);
fifo_40_wr_en_inst: fifo_0_wr_en port map (
clk => dqs4_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div1,
rst_dqs_delay_n => rst_dqs_delay_4_n,
dout => fifo_40_wr_en
);
fifo_41_wr_en_inst: fifo_1_wr_en port map (
clk => dqs4_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_4_n,
reset => reset_r,
din => rst_dqs_div1,
dout => fifo_41_wr_en
);
fifo_50_wr_en_inst: fifo_0_wr_en port map (
clk => dqs5_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div1,
rst_dqs_delay_n => rst_dqs_delay_5_n,
dout => fifo_50_wr_en
);
fifo_51_wr_en_inst: fifo_1_wr_en port map (
clk => dqs5_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_5_n,
reset => reset_r,
din => rst_dqs_div1,
dout => fifo_51_wr_en
);
fifo_60_wr_en_inst: fifo_0_wr_en port map (
clk => dqs6_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div1,
rst_dqs_delay_n => rst_dqs_delay_6_n,
dout => fifo_60_wr_en
);
fifo_61_wr_en_inst: fifo_1_wr_en port map (
clk => dqs6_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_6_n,
reset => reset_r,
din => rst_dqs_div1,
dout => fifo_61_wr_en
);
fifo_70_wr_en_inst: fifo_0_wr_en port map (
clk => dqs7_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div1,
rst_dqs_delay_n => rst_dqs_delay_7_n,
dout => fifo_70_wr_en
);
fifo_71_wr_en_inst: fifo_1_wr_en port map (
clk => dqs7_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_7_n,
reset => reset_r,
din => rst_dqs_div1,
dout => fifo_71_wr_en
);
fifo_80_wr_en_inst: fifo_0_wr_en port map (
clk => dqs8_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div2,
rst_dqs_delay_n => rst_dqs_delay_8_n,
dout => fifo_80_wr_en
);
fifo_81_wr_en_inst: fifo_1_wr_en port map (
clk => dqs8_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_8_n,
reset => reset_r,
din => rst_dqs_div2,
dout => fifo_81_wr_en
);
fifo_90_wr_en_inst: fifo_0_wr_en port map (
clk => dqs9_delayed_col1_n,
rst_dqs_delay_n => rst_dqs_delay_9_n,
reset => reset_r,
din => rst_dqs_div2,
dout => fifo_90_wr_en
);
fifo_91_wr_en_inst: fifo_1_wr_en port map (
clk => dqs9_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_9_n,
reset => reset_r,
din => rst_dqs_div2,
dout => fifo_91_wr_en
);
fifo_100_wr_en_inst: fifo_0_wr_en port map (
clk => dqs10_delayed_col1_n,
rst_dqs_delay_n => rst_dqs_delay_10_n,
reset => reset_r,
din => rst_dqs_div2,
dout => fifo_100_wr_en
);
fifo_101_wr_en_inst: fifo_1_wr_en port map (
clk => dqs10_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_10_n,
reset => reset_r,
din => rst_dqs_div2,
dout => fifo_101_wr_en
);
fifo_110_wr_en_inst: fifo_0_wr_en port map (
clk => dqs11_delayed_col1_n,
rst_dqs_delay_n => rst_dqs_delay_11_n,
reset => reset_r,
din => rst_dqs_div2,
dout => fifo_110_wr_en
);
fifo_111_wr_en_inst: fifo_1_wr_en port map (
clk => dqs11_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_11_n,
reset => reset_r,
din => rst_dqs_div2,
dout => fifo_111_wr_en
);
fifo_120_wr_en_inst: fifo_0_wr_en port map (
clk => dqs12_delayed_col1_n,
rst_dqs_delay_n => rst_dqs_delay_12_n,
reset => reset_r,
din => rst_dqs_div2,
dout => fifo_120_wr_en
);
fifo_121_wr_en_inst: fifo_1_wr_en port map (
clk => dqs12_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_12_n,
reset => reset_r,
din => rst_dqs_div2,
dout => fifo_121_wr_en
);
fifo_130_wr_en_inst: fifo_0_wr_en port map (
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