📄 data_read_24bit.vhd
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--*********************************************************************
-- DDR 24 Bit Controller DATA PATH for LEFT RIGHT Pins
-- In the current DATA PATH logic DATA CAPTURE part was modified.
-- The below changes were made to reduce the resources in
-- the data capture
-- in the current architecture data ( dq ) from ddr memory
-- directly stored into the FIFO's.
-- Architectural changes :
-- Used only TWO FIFOs ( instead of FOUR FIFOs )
-- Used Single col ( col0 ) dqs_delayed_col signals
-- Used Gray Counters for write and read pointers of the FIFOs
-- fbit stage is removed from ddr1_dqbit module ( in the data capture )
-- dq_clk stage was removed
-- dqs_clk_div logic was removed
-- ddr1_transfer_done logic was removed
-- data valid signals registering in clk90 domain was removed
-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic
-- write enable for the FIFOs derived from rst_dqs_div signal
-- Code revised by : Narayana Murty.
-- Date : Nov 18, 2003.
--*********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify;
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity data_read_24bit is
port(
clk90 : in std_logic;
reset90_r : in std_logic;
ddr_dq_in : in std_logic_vector(23 downto 0);
read_valid_data_1 : in std_logic;
fifo_00_wr_en : in std_logic;
fifo_10_wr_en : in std_logic;
fifo_20_wr_en : in std_logic;
fifo_01_wr_en : in std_logic;
fifo_11_wr_en : in std_logic;
fifo_21_wr_en : in std_logic;
fifo_00_wr_addr : in std_logic_vector(3 downto 0);
fifo_01_wr_addr : in std_logic_vector(3 downto 0);
fifo_10_wr_addr : in std_logic_vector(3 downto 0);
fifo_11_wr_addr : in std_logic_vector(3 downto 0);
fifo_20_wr_addr : in std_logic_vector(3 downto 0);
fifo_21_wr_addr : in std_logic_vector(3 downto 0);
dqs0_delayed_col1 : in std_logic;
dqs1_delayed_col1 : in std_logic;
dqs2_delayed_col1 : in std_logic;
dqs0_delayed_col0 : in std_logic;
dqs1_delayed_col0 : in std_logic;
dqs2_delayed_col0 : in std_logic;
user_output_data : out std_logic_vector(47 downto 0);
fifo0_rd_addr_val: out std_logic_vector(3 downto 0);
fifo1_rd_addr_val: out std_logic_vector(3 downto 0)
);
end data_read_24bit;
architecture arc_data_read of data_read_24bit is
attribute syn_noprune : boolean; -- Using syn_noprune Derictive
attribute syn_preserve : boolean; -- Using syn_noprune Derictive
-- rd_gray_cntr is a gray counter with a SYNC reset ( reset_90r) for fifo rd_addr
component rd_gray_cntr port (
clk : in std_logic;
reset : in std_logic;
cnt_en : in std_logic;
rgc_gcnt : out std_logic_vector(3 downto 0)
);
end component;
component FD port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
-- 16x1 Dual Port RAM Component Instansiated
component RAM16X1D
port (D : in std_logic;
WE : in std_logic;
WCLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
SPO : out std_logic;
DPO : out std_logic);
end component;
signal read_valid_data_1_r : std_logic;
signal read_valid_data_1_r1 : std_logic;
signal read_valid_data_1_r2 : std_logic;
signal fifo00_rd_addr : std_logic_vector(3 downto 0);
signal fifo01_rd_addr : std_logic_vector(3 downto 0);
signal fifo00_rd_addr_r : std_logic_vector(3 downto 0);
signal fifo01_rd_addr_r : std_logic_vector(3 downto 0);
signal fifo10_rd_addr_r : std_logic_vector(3 downto 0);
signal fifo11_rd_addr_r : std_logic_vector(3 downto 0);
signal fifo20_rd_addr_r : std_logic_vector(3 downto 0);
signal fifo21_rd_addr_r : std_logic_vector(3 downto 0);
signal fifop_rd_addr_r : std_logic_vector(3 downto 0);
attribute syn_noprune of fifo00_rd_addr_r : signal is true;
attribute syn_noprune of fifo01_rd_addr_r : signal is true;
attribute syn_noprune of fifo10_rd_addr_r : signal is true;
attribute syn_noprune of fifo11_rd_addr_r : signal is true;
attribute syn_noprune of fifo20_rd_addr_r : signal is true;
attribute syn_noprune of fifo21_rd_addr_r : signal is true;
attribute syn_noprune of fifop_rd_addr_r : signal is true;
attribute syn_preserve of fifo00_rd_addr_r : signal is true;
attribute syn_preserve of fifo01_rd_addr_r : signal is true;
attribute syn_preserve of fifo10_rd_addr_r : signal is true;
attribute syn_preserve of fifo11_rd_addr_r : signal is true;
attribute syn_preserve of fifo20_rd_addr_r : signal is true;
attribute syn_preserve of fifo21_rd_addr_r : signal is true;
attribute syn_preserve of fifop_rd_addr_r : signal is true;
signal fifo_00_data_out : std_logic_vector(7 downto 0);
signal fifo_01_data_out : std_logic_vector(7 downto 0);
signal fifo_10_data_out : std_logic_vector(7 downto 0);
signal fifo_11_data_out : std_logic_vector(7 downto 0);
signal fifo_20_data_out : std_logic_vector(7 downto 0);
signal fifo_21_data_out : std_logic_vector(7 downto 0);
-- reg added for timing
signal fifo_00_data_out_r : std_logic_vector(7 downto 0);
signal fifo_01_data_out_r : std_logic_vector(7 downto 0);
signal fifo_10_data_out_r : std_logic_vector(7 downto 0);
signal fifo_11_data_out_r : std_logic_vector(7 downto 0);
signal fifo_20_data_out_r : std_logic_vector(7 downto 0);
signal fifo_21_data_out_r : std_logic_vector(7 downto 0);
signal first_sdr_data : std_logic_vector(47 downto 0);
signal dqs0_delayed_col0_n : std_logic;
signal dqs1_delayed_col0_n : std_logic;
signal dqs2_delayed_col0_n : std_logic;
-- Directive for synthesis
--attribute syn_noprune of dqs0_delayed_col0_n : signal is true;
--attribute syn_noprune of dqs1_delayed_col0_n : signal is true;
--attribute syn_noprune of dqs2_delayed_col0_n : signal is true;
signal dqs0_delayed_col1_n : std_logic;
signal dqs1_delayed_col1_n : std_logic;
signal dqs2_delayed_col1_n : std_logic;
-- Directive for synthesis
--attribute syn_noprune of dqs0_delayed_col1_n : signal is true;
--attribute syn_noprune of dqs1_delayed_col1_n : signal is true;
--attribute syn_noprune of dqs2_delayed_col1_n : signal is true;
begin
dqs0_delayed_col0_n <= not dqs0_delayed_col0;
dqs1_delayed_col0_n <= not dqs1_delayed_col0;
dqs2_delayed_col0_n <= not dqs2_delayed_col0;
dqs0_delayed_col1_n <= not dqs0_delayed_col1;
dqs1_delayed_col1_n <= not dqs1_delayed_col1;
dqs2_delayed_col1_n <= not dqs2_delayed_col1;
user_output_data <= first_sdr_data;
fifo0_rd_addr_val <= fifo01_rd_addr;
fifo1_rd_addr_val <= fifo00_rd_addr;
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
fifo_00_data_out_r <= "00000000";
fifo_01_data_out_r <= "00000000";
fifo_10_data_out_r <= "00000000";
fifo_11_data_out_r <= "00000000";
fifo_20_data_out_r <= "00000000";
fifo_21_data_out_r <= "00000000";
else
fifo_00_data_out_r <= fifo_00_data_out;
fifo_01_data_out_r <= fifo_01_data_out;
fifo_10_data_out_r <= fifo_10_data_out;
fifo_11_data_out_r <= fifo_11_data_out;
fifo_20_data_out_r <= fifo_20_data_out;
fifo_21_data_out_r <= fifo_21_data_out;
end if;
end if;
end process;
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
fifo00_rd_addr_r <= "0000";
fifo01_rd_addr_r <= "0000";
fifo10_rd_addr_r <= "0000";
fifo11_rd_addr_r <= "0000";
fifo20_rd_addr_r <= "0000";
fifo21_rd_addr_r <= "0000";
fifop_rd_addr_r <= "0000";
else
fifo00_rd_addr_r <= fifo00_rd_addr;
fifo01_rd_addr_r <= fifo00_rd_addr;
fifo10_rd_addr_r <= fifo00_rd_addr;
fifo11_rd_addr_r <= fifo00_rd_addr;
fifo20_rd_addr_r <= fifo00_rd_addr;
fifo21_rd_addr_r <= fifo00_rd_addr;
fifop_rd_addr_r <= fifo01_rd_addr;
end if;
end if;
end process;
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
first_sdr_data <= (others => '0');
read_valid_data_1_r <= '0';
read_valid_data_1_r1 <= '0';
read_valid_data_1_r2 <= '0';
else
read_valid_data_1_r <= read_valid_data_1;
read_valid_data_1_r1 <= read_valid_data_1_r;
read_valid_data_1_r2 <= read_valid_data_1_r1;
if (read_valid_data_1_r1 = '1') then
first_sdr_data <=
( fifo_20_data_out_r & fifo_10_data_out_r &
fifo_00_data_out_r & fifo_21_data_out_r & fifo_11_data_out_r &
fifo_01_data_out_r );
else
first_sdr_data <= first_sdr_data;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )
fifo0_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_1,
rgc_gcnt => fifo00_rd_addr
);
fifo1_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_1,
rgc_gcnt => fifo01_rd_addr
);
--*************************************************************************************************************************
-- Dual Port RAM 16x1 instantiations (fifo0 -- Positive edge, fifo1 -- Trailing edge)
--*************************************************************************************************************************
--- Byte0 instantiation
fifo0_bit0 : RAM16X1D
port map (DPO => fifo_00_data_out(0),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(0),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1,
WE => fifo_00_wr_en );
fifo1_bit0 : RAM16X1D
port map (DPO => fifo_01_data_out(0),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
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