data_read_controller_24bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

process (clk90)                                            
begin                                                      
  if (rising_edge(clk90)) then                             
    if (reset90_r = '1') then                                 
 		fifo_00_wr_addr_d <= "0000";
		fifo_01_wr_addr_d <= "0000";
    else                                                   
    	fifo_00_wr_addr_d <= fifo_00_wr_addr;
		fifo_01_wr_addr_d <= fifo_01_wr_addr;
    end if;                                                
  end if;                                                  
end process;              


-- FIFO WRITE POINTER DOUBLE DELAYED SIGNALS

process (clk90)                                            
begin                                                      
  if (rising_edge(clk90)) then                             
    if (reset90_r = '1') then                                 
		fifo_00_wr_addr_2d <= "0000";
		fifo_01_wr_addr_2d <= "0000";
    else                                                   
    	fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
		fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
    end if;                                                
  end if;                                                  
end process;         


-- user data valid output signal from data path.

   
     
fifo_00_empty       <= '1' when (fifo_00_rd_addr(3 downto 0) = fifo_00_wr_addr_2d(3 downto 0)) else
                       '0';
fifo_01_empty       <= '1' when (fifo_01_rd_addr(3 downto 0) = fifo_01_wr_addr_2d(3 downto 0)) else                     
                      '0';                                                                            

read_valid_data_0_1 <= ( (not fifo_00_empty) and (not fifo_01_empty) );
read_valid_data_1_val   <= read_valid_data_0_1;

process(clk90)
begin
if clk90'event and clk90 = '1' then
 	if reset90_r = '1' then
		u_data_val	<= '0';
 	else
		u_data_val  <= read_valid_data_0_1;
	end if;
end if;
end process; 

--- Assignments done by MURTHY
--  here vector component is assigned to a scalar signal
--  it was done because the delay_dqs signals were used 

dqs0_delayed_col0 <= dqs_delayed_col0(0);
dqs1_delayed_col0 <= dqs_delayed_col0(1);
dqs2_delayed_col0 <= dqs_delayed_col0(2);

-- dqsx_delayed_col0 negated signals

dqs0_delayed_col0_n <= not dqs0_delayed_col0;
dqs1_delayed_col0_n <= not dqs1_delayed_col0;
dqs2_delayed_col0_n <= not dqs2_delayed_col0;

rst_dqs_div_delayed : dqs_delay port map (                                                                          
	                              clk_in   => rst_dqs_div_in,
	                              sel_in   => delay_sel,                                
	                              clk_out  => rst_dqs_div                              
	                             );
--------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------

-- fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )  

fifo_00_rd_addr_inst :   rd_gray_cntr port map (
							clk 		=>	clk90,
							reset		=>	reset90_r,
							cnt_en	=>	read_valid_data_0_1,
							rgc_gcnt	=>	fifo_00_rd_addr
						); 

fifo_10_rd_addr_inst :   rd_gray_cntr port map (
							clk 		=>	clk90,
							reset		=>	reset90_r,
							cnt_en	=>	read_valid_data_0_1,
							rgc_gcnt	=>	fifo_10_rd_addr
						); 
fifo_20_rd_addr_inst :   rd_gray_cntr port map (
							clk 		=>	clk90,
							reset		=>	reset90_r,
							cnt_en	=>	read_valid_data_0_1,
							rgc_gcnt	=>	fifo_20_rd_addr
						); 

fifo_01_rd_addr_inst :   rd_gray_cntr port map (
							clk 		=>	clk90,
							reset		=>	reset90_r,
							cnt_en	=>	read_valid_data_0_1,
							rgc_gcnt	=>	fifo_01_rd_addr
						); 

fifo_11_rd_addr_inst :   rd_gray_cntr port map (
							clk 		=>	clk90,
							reset		=>	reset90_r,
							cnt_en	=>	read_valid_data_0_1,
							rgc_gcnt	=>	fifo_11_rd_addr
						); 
fifo_21_rd_addr_inst :   rd_gray_cntr port map (
							clk 		=>	clk90,
							reset		=>	reset90_r,
							cnt_en	=>	read_valid_data_0_1,
							rgc_gcnt	=>	fifo_21_rd_addr
						); 

--**************************************************************************************************
-- DQS Internal Delay Circuit implemented in LUTs
--**************************************************************************************************

-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay0_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in0,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(0)                               
	                             );

                    
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay1_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in1,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(1)                               
	                             );

                    
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay2_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in2,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(2)                               
	                             );
-------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------

-- FIFO Write enable signal generation

-- FIFO Write enable signal generation

fifo_00_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs0_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_0_n,
						dout		=> fifo_00_wr_en
				   	   );

fifo_01_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs0_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_01_wr_en
				          );

fifo_10_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs1_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_1_n,
						dout		=> fifo_10_wr_en
				   	   );

fifo_11_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs1_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_1_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_11_wr_en
				          );


fifo_20_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs2_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_2_n,
						dout		=> fifo_20_wr_en
				   	   );

fifo_21_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs2_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_2_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_21_wr_en
				          );

-------------------------------------------------------------------------------------------------
-- write pointer gray counter instances 

fifo_00_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs0_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_00_wr_en,
							wgc_gcnt		=>	fifo_00_wr_addr
						);

fifo_01_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs0_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_01_wr_en,
							wgc_gcnt		=>	fifo_01_wr_addr
						);


fifo_10_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs1_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_10_wr_en,
							wgc_gcnt		=>	fifo_10_wr_addr
						);


fifo_11_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs1_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_11_wr_en,
							wgc_gcnt		=>	fifo_11_wr_addr
						);

fifo_20_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs2_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_20_wr_en,
							wgc_gcnt		=>	fifo_20_wr_addr
						);


fifo_21_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs2_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_21_wr_en,
							wgc_gcnt		=>	fifo_21_wr_addr
						);
end   arc_data_read_controller_24bit;