iobs.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;
use work.parameter_16bit.all; 
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity iobs is
port(
     SYS_CLK           : in std_logic;
     SYS_CLKb          : in std_logic;
     clk               : in std_logic;
     clk90             : in std_logic;  
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
     rst_dqs_div_int   : in std_logic;
     dqs_reset         : in std_logic;
     dqs_enable        : in std_logic;
     ddr_dqs           : inout std_logic_vector(1 downto 0);
     ddr_dq            : inout std_logic_vector(15 downto 0);
     write_data_falling: in std_logic_vector(15 downto 0);
     write_data_rising : in std_logic_vector(15 downto 0);
     write_en_val      : in std_logic;
     reset90_r         : in std_logic;
     data_mask_f       : in std_logic_vector(1 downto 0);
     data_mask_r       : in std_logic_vector(1 downto 0);
     sys_clk_ibuf      : out std_logic;
     rst_dqs_div       : out std_logic;
     rst_dqs_div_in    : in std_logic;
     rst_dqs_div_out   : out std_logic;
     dqs_int_delay_in0 : out std_logic;
     dqs_int_delay_in1 : out std_logic;
     dq                : out std_logic_vector(15 downto 0);
     ddr_dm            : out std_logic_vector(1 downto 0)              
);
end iobs;


architecture arc_iobs of iobs is

component infrastructure_iobs 
 port(
      SYS_CLK           : in STD_LOGIC;
      SYS_CLKb          : in STD_LOGIC;
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
      rst_dqs_div_int   : in std_logic;
      rst_dqs_div       : out std_logic;
      rst_dqs_div_in    : in std_logic;
      rst_dqs_div_out   : out std_logic;      
      sys_clk_ibuf      : out STD_LOGIC
      );
end component;

component data_path_iobs_16bit 
port(
    clk               : in std_logic;
    clk90             : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
    reset90_r         : in std_logic;
    dqs_reset         : in std_logic;
    dqs_enable        : in std_logic;
    ddr_dqs           : inout std_logic_vector(1 downto 0);
    ddr_dq            : inout std_logic_vector(15 downto 0);
    write_data_falling: in std_logic_vector(15 downto 0);
    write_data_rising : in std_logic_vector(15 downto 0);
    write_en_val      : in std_logic;
    data_mask_f       : in std_logic_vector(1 downto 0);
    data_mask_r       : in std_logic_vector(1 downto 0);
    dqs_int_delay_in0 : out std_logic;
    dqs_int_delay_in1 : out std_logic;
    ddr_dq_val        : out std_logic_vector(15 downto 0);
    ddr_dm            : out std_logic_vector(1 downto 0)  
);
end component;


begin

infrastructure_iobs0 : infrastructure_iobs port map (
                                                     SYS_CLK          => SYS_CLK,
                                                     SYS_CLKb         => SYS_CLKb,
				      --XST_REMOVECOMMENT    clk180          => clk180,
					--XST_REMOVECOMMENT    clk270          => clk270,
                                                     rst_dqs_div_int  => rst_dqs_div_int,
                                                     rst_dqs_div      => rst_dqs_div, 
                                                     rst_dqs_div_in   => rst_dqs_div_in,
                                                     rst_dqs_div_out  => rst_dqs_div_out,
                                                     sys_clk_ibuf     => sys_clk_ibuf
                                                    );


datapath_iobs0 : data_path_iobs_16bit port map (
                                         clk                =>   clk,	
					 clk90              =>   clk90,																	 
				      --XST_REMOVECOMMENT    clk180          => clk180,
					--XST_REMOVECOMMENT    clk270          => clk270,
					 reset90_r          =>   reset90_r,
                                         dqs_reset          =>   dqs_reset,
                                         dqs_enable         =>   dqs_enable,
                                         ddr_dqs            =>   ddr_dqs(1 downto 0),
                                         ddr_dq             =>   ddr_dq(15 downto 0),
                                         write_data_falling =>   write_data_falling(15 downto 0),
                                         write_data_rising  =>   write_data_rising(15 downto 0),
                                         write_en_val       =>   write_en_val,
                                         data_mask_f        =>   data_mask_f(1 downto 0),
                                         data_mask_r        =>   data_mask_r(1 downto 0),
                                         dqs_int_delay_in0  =>   dqs_int_delay_in0,
                                         dqs_int_delay_in1  =>   dqs_int_delay_in1,
                                         ddr_dq_val         =>   dq(15 downto 0),
                                         ddr_dm             =>   ddr_dm(1 downto 0)
                                        );

   

end arc_iobs;