data_read_controller_16bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

-- dqsx_delayed_col1 negated signals

dqs0_delayed_col1_n <= not dqs0_delayed_col1;
dqs1_delayed_col1_n <= not dqs1_delayed_col1;

-- data_valid signal is derived from fifo_00 and fifo_01 empty signals only
-- FIFO WRITE POINTER DELAYED SIGNALS
-- To avoid meta-stability due to the domain crossing from ddr_dqs to clk90 

process (clk90)                                            
begin                                                      
  if (rising_edge(clk90)) then                             
    if (reset90_r = '1') then                                 
 		fifo_00_wr_addr_d <= "0000";
		fifo_01_wr_addr_d <= "0000";
 
    else                                                   
    	fifo_00_wr_addr_d <= fifo_00_wr_addr;
		fifo_01_wr_addr_d <= fifo_01_wr_addr;

    end if;                                                
  end if;                                                  
end process;              


-- FIFO WRITE POINTER DOUBLE DELAYED SIGNALS

process (clk90)                                            
begin                                                      
  if (rising_edge(clk90)) then                             
    if (reset90_r = '1') then                                 
		fifo_00_wr_addr_2d <= "0000";
		fifo_01_wr_addr_2d <= "0000";
    else                                                   
    	        fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
		fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
    end if;                                                
  end if;                                                  
end process;         


process (clk90)                                            
begin                                                      
  if (rising_edge(clk90)) then                             
    if (reset90_r = '1') then                                 
		fifo_00_wr_addr_3d <= "0000";
		fifo_01_wr_addr_3d <= "0000";
    else                                                   
    	        fifo_00_wr_addr_3d <= fifo_00_wr_addr_2d;
		fifo_01_wr_addr_3d <= fifo_01_wr_addr_2d;
    end if;                                                
  end if;                                                  
end process;         
-- user data valid output signal from data path.
     
fifo_00_empty       <= '1' when (fifo0_rd_addr(3 downto 0) = fifo_00_wr_addr_3d(3 downto 0)) else  '0';
fifo_01_empty       <= '1' when (fifo1_rd_addr(3 downto 0) = fifo_01_wr_addr_3d(3 downto 0)) else  '0';   
                                                                         



read_valid_data_0_1 <= ( (not fifo_00_empty) and (not fifo_01_empty) );
read_valid_data_1_val   <= (read_valid_data_0_1);



process(clk90)
begin
if clk90'event and clk90 = '1' then
 	if reset90_r = '1' then
		u_data_val	<= '0';
                read_valid_data_r <= '0';
                read_valid_data_r1 <= '0';
                

 	else
                read_valid_data_r <= read_valid_data_0_1;
                read_valid_data_r1 <= read_valid_data_r;
		u_data_val  <= read_valid_data_r1;
	end if;
end if;
end process; 



--- Assignments done by MURTHY
--  here vector component is assigned to a scalar signal
--  it was done because the delay_dqs signals were used 

dqs0_delayed_col0 <= dqs_delayed_col0(0);
dqs1_delayed_col0 <= dqs_delayed_col0(1);

---- Added on JAN28 ----

dqs0_delayed_col1 <= dqs_delayed_col1(0);
dqs1_delayed_col1 <= dqs_delayed_col1(1);

-- dqsx_delayed_col0 negated signals





rst_dqs_div_delayed1 : dqs_delay port map (                                                                          
	                              clk_in   => rst_dqs_div_in,
	                              sel_in   => delay_sel,                                
	                              clk_out  => rst_dqs_div                              
	                             );





--------------------------------------------------------------------------------------------------------------------------------------------------
--**************************************************************************************************
-- DQS Internal Delay Circuit implemented in LUTs
--**************************************************************************************************

-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay0_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in0,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(0)                               
	                             );

-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs                               
dqs_delay0_col1 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in0,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col1(0)                               
	                             );
                    
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay1_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in1,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(1)                               
	                             );

-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs                               
dqs_delay1_col1 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in1,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col1(1)                               
	                             );


-------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------

fifo_00_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs0_delayed_col1_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_0_n,
						dout		=> fifo_00_wr_en
				   	   );


fifo_01_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs0_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_01_wr_en
				          );


fifo_10_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs1_delayed_col1_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_1_n,
						dout		=> fifo_10_wr_en
				   	   );


fifo_11_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs1_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_1_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_11_wr_en
				          );


-------------------------------------------------------------------------------------------------
-- write pointer gray counter instances 

fifo_00_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs0_delayed_col1,
							reset		=>	reset_r,
							cnt_en	        =>	fifo_00_wr_en,
                                                        
							wgc_gcnt        =>	fifo_00_wr_addr
						);

fifo_01_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs0_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	        =>	fifo_01_wr_en,
                                                        
							wgc_gcnt        =>	fifo_01_wr_addr
						);


fifo_10_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs1_delayed_col1,
							reset		=>	reset_r,
							cnt_en	        =>	fifo_10_wr_en,
                                                        
							wgc_gcnt	=>	fifo_10_wr_addr
						);


fifo_11_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs1_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	        =>	fifo_11_wr_en,
                                                        
							wgc_gcnt	=>	fifo_11_wr_addr
						);


end arc_data_read_controller;