📄 data_read_16bit.vhd
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port map (DPO => fifo_00_data_out(3),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(3),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit3 : RAM16X1D
port map (DPO => fifo_01_data_out(3),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(3),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
fifo0_bit4 : RAM16X1D
port map (DPO => fifo_00_data_out(4),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(4),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1,
WE => fifo_00_wr_en );
fifo1_bit4 : RAM16X1D
port map (DPO => fifo_01_data_out(4),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(4),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1_n,
WE => fifo_01_wr_en );
fifo0_bit5 : RAM16X1D
port map (DPO => fifo_00_data_out(5),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(5),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit5 : RAM16X1D
port map (DPO => fifo_01_data_out(5),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(5),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
fifo0_bit6 : RAM16X1D
port map (DPO => fifo_00_data_out(6),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(6),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1,
WE => fifo_00_wr_en );
fifo1_bit6 : RAM16X1D
port map (DPO => fifo_01_data_out(6),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(6),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1_n,
WE => fifo_01_wr_en );
fifo0_bit7 : RAM16X1D
port map (DPO => fifo_00_data_out(7),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(7),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit7 : RAM16X1D
port map (DPO => fifo_01_data_out(7),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(7),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
-- Byte1 Fifo instantiation
fifo0_bit8 : RAM16X1D
port map (DPO => fifo_10_data_out(0),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(8),
DPRA0 => fifo10_rd_addr_r(0),
DPRA1 => fifo10_rd_addr_r(1),
DPRA2 => fifo10_rd_addr_r(2),
DPRA3 => fifo10_rd_addr_r(3),
WCLK => dqs1_delayed_col1,
WE => fifo_10_wr_en );
fifo1_bit8 : RAM16X1D
port map (DPO => fifo_11_data_out(0),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(8),
DPRA0 => fifo10_rd_addr_r(0),
DPRA1 => fifo10_rd_addr_r(1),
DPRA2 => fifo10_rd_addr_r(2),
DPRA3 => fifo10_rd_addr_r(3),
WCLK => dqs1_delayed_col1_n,
WE => fifo_11_wr_en );
fifo0_bit9 : RAM16X1D
port map (DPO => fifo_10_data_out(1),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(9),
DPRA0 => fifo11_rd_addr_r(0),
DPRA1 => fifo11_rd_addr_r(1),
DPRA2 => fifo11_rd_addr_r(2),
DPRA3 => fifo11_rd_addr_r(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit9 : RAM16X1D
port map (DPO => fifo_11_data_out(1),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(9),
DPRA0 => fifo11_rd_addr_r(0),
DPRA1 => fifo11_rd_addr_r(1),
DPRA2 => fifo11_rd_addr_r(2),
DPRA3 => fifo11_rd_addr_r(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
fifo0_bit10 : RAM16X1D
port map (DPO => fifo_10_data_out(2),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(10),
DPRA0 => fifo10_rd_addr_r(0),
DPRA1 => fifo10_rd_addr_r(1),
DPRA2 => fifo10_rd_addr_r(2),
DPRA3 => fifo10_rd_addr_r(3),
WCLK => dqs1_delayed_col1,
WE => fifo_10_wr_en );
fifo1_bit10 : RAM16X1D
port map (DPO => fifo_11_data_out(2),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(10),
DPRA0 => fifo10_rd_addr_r(0),
DPRA1 => fifo10_rd_addr_r(1),
DPRA2 => fifo10_rd_addr_r(2),
DPRA3 => fifo10_rd_addr_r(3),
WCLK => dqs1_delayed_col1_n,
WE => fifo_11_wr_en );
fifo0_bit11 : RAM16X1D
port map (DPO => fifo_10_data_out(3),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(11),
DPRA0 => fifo11_rd_addr_r(0),
DPRA1 => fifo11_rd_addr_r(1),
DPRA2 => fifo11_rd_addr_r(2),
DPRA3 => fifo11_rd_addr_r(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit11 : RAM16X1D
port map (DPO => fifo_11_data_out(3),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(11),
DPRA0 => fifo11_rd_addr_r(0),
DPRA1 => fifo11_rd_addr_r(1),
DPRA2 => fifo11_rd_addr_r(2),
DPRA3 => fifo11_rd_addr_r(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
fifo0_bit12 : RAM16X1D
port map (DPO => fifo_10_data_out(4),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(12),
DPRA0 => fifo10_rd_addr_r(0),
DPRA1 => fifo10_rd_addr_r(1),
DPRA2 => fifo10_rd_addr_r(2),
DPRA3 => fifo10_rd_addr_r(3),
WCLK => dqs1_delayed_col1,
WE => fifo_10_wr_en );
fifo1_bit12 : RAM16X1D
port map (DPO => fifo_11_data_out(4),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(12),
DPRA0 => fifo10_rd_addr_r(0),
DPRA1 => fifo10_rd_addr_r(1),
DPRA2 => fifo10_rd_addr_r(2),
DPRA3 => fifo10_rd_addr_r(3),
WCLK => dqs1_delayed_col1_n,
WE => fifo_11_wr_en );
fifo0_bit13 : RAM16X1D
port map (DPO => fifo_10_data_out(5),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(13),
DPRA0 => fifo11_rd_addr_r(0),
DPRA1 => fifo11_rd_addr_r(1),
DPRA2 => fifo11_rd_addr_r(2),
DPRA3 => fifo11_rd_addr_r(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit13 : RAM16X1D
port map (DPO => fifo_11_data_out(5),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(13),
DPRA0 => fifo11_rd_addr_r(0),
DPRA1 => fifo11_rd_addr_r(1),
DPRA2 => fifo11_rd_addr_r(2),
DPRA3 => fifo11_rd_addr_r(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
fifo0_bit14 : RAM16X1D
port map (DPO => fifo_10_data_out(6),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(14),
DPRA0 => fifo10_rd_addr_r(0),
DPRA1 => fifo10_rd_addr_r(1),
DPRA2 => fifo10_rd_addr_r(2),
DPRA3 => fifo10_rd_addr_r(3),
WCLK => dqs1_delayed_col1,
WE => fifo_10_wr_en );
fifo1_bit14 : RAM16X1D
port map (DPO => fifo_11_data_out(6),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(14),
DPRA0 => fifo10_rd_addr_r(0),
DPRA1 => fifo10_rd_addr_r(1),
DPRA2 => fifo10_rd_addr_r(2),
DPRA3 => fifo10_rd_addr_r(3),
WCLK => dqs1_delayed_col1_n,
WE => fifo_11_wr_en );
fifo0_bit15 : RAM16X1D
port map (DPO => fifo_10_data_out(7),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(15),
DPRA0 => fifo11_rd_addr_r(0),
DPRA1 => fifo11_rd_addr_r(1),
DPRA2 => fifo11_rd_addr_r(2),
DPRA3 => fifo11_rd_addr_r(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit15 : RAM16X1D
port map (DPO => fifo_11_data_out(7),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(15),
DPRA0 => fifo11_rd_addr_r(0),
DPRA1 => fifo11_rd_addr_r(1),
DPRA2 => fifo11_rd_addr_r(2),
DPRA3 => fifo11_rd_addr_r(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
end arc_data_read;
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