📄 data_read_controller_56bit.vhd
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signal fifo_10_rd_addr : std_logic_vector(3 downto 0);
signal fifo_11_rd_addr : std_logic_vector(3 downto 0);
signal fifo_20_rd_addr : std_logic_vector(3 downto 0);
signal fifo_21_rd_addr : std_logic_vector(3 downto 0);
signal fifo_30_rd_addr : std_logic_vector(3 downto 0);
signal fifo_31_rd_addr : std_logic_vector(3 downto 0);
signal fifo_40_rd_addr : std_logic_vector(3 downto 0);
signal fifo_41_rd_addr : std_logic_vector(3 downto 0);
signal fifo_50_rd_addr : std_logic_vector(3 downto 0);
signal fifo_51_rd_addr : std_logic_vector(3 downto 0);
signal fifo_60_rd_addr : std_logic_vector(3 downto 0);
signal fifo_61_rd_addr : std_logic_vector(3 downto 0);
begin
fifo_00_wr_addr_val <= fifo_00_wr_addr;
fifo_01_wr_addr_val <= fifo_01_wr_addr;
fifo_10_wr_addr_val <= fifo_10_wr_addr;
fifo_11_wr_addr_val <= fifo_11_wr_addr;
fifo_20_wr_addr_val <= fifo_20_wr_addr;
fifo_21_wr_addr_val <= fifo_21_wr_addr;
fifo_30_wr_addr_val <= fifo_30_wr_addr;
fifo_31_wr_addr_val <= fifo_31_wr_addr;
fifo_40_wr_addr_val <= fifo_40_wr_addr;
fifo_41_wr_addr_val <= fifo_41_wr_addr;
fifo_50_wr_addr_val <= fifo_50_wr_addr;
fifo_51_wr_addr_val <= fifo_51_wr_addr;
fifo_60_wr_addr_val <= fifo_60_wr_addr;
fifo_61_wr_addr_val <= fifo_61_wr_addr;
fifo_00_wr_en_val <= fifo_00_wr_en;
fifo_10_wr_en_val <= fifo_10_wr_en;
fifo_20_wr_en_val <= fifo_20_wr_en;
fifo_30_wr_en_val <= fifo_30_wr_en;
fifo_40_wr_en_val <= fifo_40_wr_en;
fifo_50_wr_en_val <= fifo_50_wr_en;
fifo_60_wr_en_val <= fifo_60_wr_en;
fifo_01_wr_en_val <= fifo_01_wr_en;
fifo_11_wr_en_val <= fifo_11_wr_en;
fifo_21_wr_en_val <= fifo_21_wr_en;
fifo_31_wr_en_val <= fifo_31_wr_en;
fifo_41_wr_en_val <= fifo_41_wr_en;
fifo_51_wr_en_val <= fifo_51_wr_en;
fifo_61_wr_en_val <= fifo_61_wr_en;
dqs0_delayed_col1_val <= dqs0_delayed_col1;
dqs1_delayed_col1_val <= dqs1_delayed_col1;
dqs2_delayed_col1_val <= dqs2_delayed_col1;
dqs3_delayed_col1_val <= dqs3_delayed_col1;
dqs4_delayed_col1_val <= dqs4_delayed_col1;
dqs5_delayed_col1_val <= dqs5_delayed_col1;
dqs6_delayed_col1_val <= dqs6_delayed_col1;
dqs0_delayed_col0_n_val <= dqs0_delayed_col0_n;
dqs1_delayed_col0_n_val <= dqs1_delayed_col0_n;
dqs2_delayed_col0_n_val <= dqs2_delayed_col0_n;
dqs3_delayed_col0_n_val <= dqs3_delayed_col0_n;
dqs4_delayed_col0_n_val <= dqs4_delayed_col0_n;
dqs5_delayed_col0_n_val <= dqs5_delayed_col0_n;
dqs6_delayed_col0_n_val <= dqs6_delayed_col0_n;
fifo_00_rd_addr_val <= fifo_00_rd_addr;
fifo_01_rd_addr_val <= fifo_01_rd_addr;
fifo_10_rd_addr_val <= fifo_10_rd_addr;
fifo_11_rd_addr_val <= fifo_11_rd_addr;
fifo_20_rd_addr_val <= fifo_20_rd_addr;
fifo_21_rd_addr_val <= fifo_21_rd_addr;
fifo_30_rd_addr_val <= fifo_30_rd_addr;
fifo_31_rd_addr_val <= fifo_31_rd_addr;
fifo_40_rd_addr_val <= fifo_40_rd_addr;
fifo_41_rd_addr_val <= fifo_41_rd_addr;
fifo_50_rd_addr_val <= fifo_50_rd_addr;
fifo_51_rd_addr_val <= fifo_51_rd_addr;
fifo_60_rd_addr_val <= fifo_60_rd_addr;
fifo_61_rd_addr_val <= fifo_61_rd_addr;
-- data_valid signal is derived from fifo_00 and fifo_01 empty signals only
-- FIFO WRITE POINTER DELAYED SIGNALS
-- To avoid meta-stability due to the domain crossing from ddr_dqs to clk90
process (clk90)
begin
if (rising_edge(clk90)) then
if (reset90_r = '1') then
fifo_00_wr_addr_d <= "0000";
fifo_01_wr_addr_d <= "0000";
else
fifo_00_wr_addr_d <= fifo_00_wr_addr;
fifo_01_wr_addr_d <= fifo_01_wr_addr;
end if;
end if;
end process;
-- FIFO WRITE POINTER DOUBLE DELAYED SIGNALS
process (clk90)
begin
if (rising_edge(clk90)) then
if (reset90_r = '1') then
fifo_00_wr_addr_2d <= "0000";
fifo_01_wr_addr_2d <= "0000";
else
fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
end if;
end if;
end process;
-- user data valid output signal from data path.
fifo_00_empty <= '1' when (fifo_00_rd_addr(3 downto 0) = fifo_00_wr_addr_2d(3 downto 0)) else
'0';
fifo_01_empty <= '1' when (fifo_01_rd_addr(3 downto 0) = fifo_01_wr_addr_2d(3 downto 0)) else
'0';
read_valid_data_0_1 <= ( (not fifo_00_empty) and (not fifo_01_empty) );
read_valid_data_1_val <= read_valid_data_0_1;
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
u_data_val <= '0';
else
u_data_val <= read_valid_data_0_1;
end if;
end if;
end process;
--- Assignments done by MURTHY
-- here vector component is assigned to a scalar signal
-- it was done because the delay_dqs signals were used
dqs0_delayed_col0 <= dqs_delayed_col0(0);
dqs1_delayed_col0 <= dqs_delayed_col0(1);
dqs2_delayed_col0 <= dqs_delayed_col0(2);
dqs3_delayed_col0 <= dqs_delayed_col0(3);
dqs4_delayed_col0 <= dqs_delayed_col0(4);
dqs5_delayed_col0 <= dqs_delayed_col0(5);
dqs6_delayed_col0 <= dqs_delayed_col0(6);
---- Added on JAN28 ----
dqs0_delayed_col1 <= dqs_delayed_col1(0);
dqs1_delayed_col1 <= dqs_delayed_col1(1);
dqs2_delayed_col1 <= dqs_delayed_col1(2);
dqs3_delayed_col1 <= dqs_delayed_col1(3);
dqs4_delayed_col1 <= dqs_delayed_col1(4);
dqs5_delayed_col1 <= dqs_delayed_col1(5);
dqs6_delayed_col1 <= dqs_delayed_col1(6);
-- dqsx_delayed_col0 negated signals
dqs0_delayed_col0_n <= not dqs0_delayed_col0;
dqs1_delayed_col0_n <= not dqs1_delayed_col0;
dqs2_delayed_col0_n <= not dqs2_delayed_col0;
dqs3_delayed_col0_n <= not dqs3_delayed_col0;
dqs4_delayed_col0_n <= not dqs4_delayed_col0;
dqs5_delayed_col0_n <= not dqs5_delayed_col0;
dqs6_delayed_col0_n <= not dqs6_delayed_col0;
-- dqsx_delayed_col1 negated signals
dqs0_delayed_col1_n <= not dqs0_delayed_col1;
dqs1_delayed_col1_n <= not dqs1_delayed_col1;
dqs2_delayed_col1_n <= not dqs2_delayed_col1;
dqs3_delayed_col1_n <= not dqs3_delayed_col1;
dqs4_delayed_col1_n <= not dqs4_delayed_col1;
dqs5_delayed_col1_n <= not dqs5_delayed_col1;
dqs6_delayed_col1_n <= not dqs6_delayed_col1;
rst_dqs_div_delayed : dqs_delay port map (
clk_in => rst_dqs_div_in,
sel_in => delay_sel,
clk_out => rst_dqs_div
);
--------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------
-- fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )
fifo_00_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_00_rd_addr
);
fifo_10_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_10_rd_addr
);
fifo_20_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_20_rd_addr
);
fifo_30_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_30_rd_addr
);
fifo_40_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_40_rd_addr
);
fifo_50_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_50_rd_addr
);
fifo_60_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_60_rd_addr
);
fifo_01_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_01_rd_addr
);
fifo_11_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_11_rd_addr
);
fifo_21_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_21_rd_addr
);
fifo_31_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_31_rd_addr
);
fifo_41_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_41_rd_addr
);
fifo_51_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_51_rd_addr
);
fifo_61_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_61_rd_addr
);
--**************************************************************************************************
-- DQS Internal Delay Circuit implemented in LUTs
--**************************************************************************************************
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay0_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in0,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(0)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay0_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in0,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(0)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay1_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in1,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(1)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay1_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in1,
sel_in => delay_sel,
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