📄 data_read_56bit.vhd
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DPRA1 => fifo_11_rd_addr(1),
DPRA2 => fifo_11_rd_addr(2),
DPRA3 => fifo_11_rd_addr(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
-- Byte2 Fifo instantiation
fifo0_bit16 : RAM16X1D
port map (DPO => fifo_20_data_out(0),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(16),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit16 : RAM16X1D
port map (DPO => fifo_21_data_out(0),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(16),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit17 : RAM16X1D
port map (DPO => fifo_20_data_out(1),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(17),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit17 : RAM16X1D
port map (DPO => fifo_21_data_out(1),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(17),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit18 : RAM16X1D
port map (DPO => fifo_20_data_out(2),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(18),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit18 : RAM16X1D
port map (DPO => fifo_21_data_out(2),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(18),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit19 : RAM16X1D
port map (DPO => fifo_20_data_out(3),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(19),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit19 : RAM16X1D
port map (DPO => fifo_21_data_out(3),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(19),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit20 : RAM16X1D
port map (DPO => fifo_20_data_out(4),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(20),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit20 : RAM16X1D
port map (DPO => fifo_21_data_out(4),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(20),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit21 : RAM16X1D
port map (DPO => fifo_20_data_out(5),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(21),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit21 : RAM16X1D
port map (DPO => fifo_21_data_out(5),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(21),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit22 : RAM16X1D
port map (DPO => fifo_20_data_out(6),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(22),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit22 : RAM16X1D
port map (DPO => fifo_21_data_out(6),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(22),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit23 : RAM16X1D
port map (DPO => fifo_20_data_out(7),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(23),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit23 : RAM16X1D
port map (DPO => fifo_21_data_out(7),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(23),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
--Byte3 Fifo Instantiation
fifo0_bit24 : RAM16X1D
port map (DPO => fifo_30_data_out(0),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(24),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit24 : RAM16X1D
port map (DPO => fifo_31_data_out(0),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(24),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit25 : RAM16X1D
port map (DPO => fifo_30_data_out(1),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(25),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit25 : RAM16X1D
port map (DPO => fifo_31_data_out(1),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(25),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit26 : RAM16X1D
port map (DPO => fifo_30_data_out(2),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(26),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit26 : RAM16X1D
port map (DPO => fifo_31_data_out(2),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(26),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
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