📄 data_read_controller_56bit.vhd
字号:
fifo_00_empty <= '1' when (fifo_00_rd_addr(3 downto 0) = fifo_00_wr_addr_2d(3 downto 0)) else
'0';
fifo_01_empty <= '1' when (fifo_01_rd_addr(3 downto 0) = fifo_01_wr_addr_2d(3 downto 0)) else
'0';
read_valid_data_0_1 <= ( (not fifo_00_empty) and (not fifo_01_empty) );
read_valid_data_1_val <= read_valid_data_0_1;
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
u_data_val <= '0';
else
u_data_val <= read_valid_data_0_1;
end if;
end if;
end process;
--- Assignments done by MURTHY
-- here vector component is assigned to a scalar signal
-- it was done because the delay_dqs signals were used
dqs0_delayed_col0 <= dqs_delayed_col0(0);
dqs1_delayed_col0 <= dqs_delayed_col0(1);
dqs2_delayed_col0 <= dqs_delayed_col0(2);
dqs3_delayed_col0 <= dqs_delayed_col0(3);
dqs4_delayed_col0 <= dqs_delayed_col0(4);
dqs5_delayed_col0 <= dqs_delayed_col0(5);
dqs6_delayed_col0 <= dqs_delayed_col0(6);
dqs7_delayed_col0 <= dqs_delayed_col0(7);
dqs8_delayed_col0 <= dqs_delayed_col0(8);
dqs9_delayed_col0 <= dqs_delayed_col0(9);
dqs10_delayed_col0 <= dqs_delayed_col0(10);
dqs11_delayed_col0 <= dqs_delayed_col0(11);
dqs12_delayed_col0 <= dqs_delayed_col0(12);
dqs13_delayed_col0 <= dqs_delayed_col0(13);
---- Added on JAN28 ----
dqs0_delayed_col1 <= dqs_delayed_col1(0);
dqs1_delayed_col1 <= dqs_delayed_col1(1);
dqs2_delayed_col1 <= dqs_delayed_col1(2);
dqs3_delayed_col1 <= dqs_delayed_col1(3);
dqs4_delayed_col1 <= dqs_delayed_col1(4);
dqs5_delayed_col1 <= dqs_delayed_col1(5);
dqs6_delayed_col1 <= dqs_delayed_col1(6);
dqs7_delayed_col1 <= dqs_delayed_col1(7);
dqs8_delayed_col1 <= dqs_delayed_col1(8);
dqs9_delayed_col1 <= dqs_delayed_col1(9);
dqs10_delayed_col1 <= dqs_delayed_col1(10);
dqs11_delayed_col1 <= dqs_delayed_col1(11);
dqs12_delayed_col1 <= dqs_delayed_col1(12);
dqs13_delayed_col1 <= dqs_delayed_col1(13);
-- dqsx_delayed_col0 negated signals
dqs0_delayed_col0_n <= not dqs0_delayed_col0;
dqs1_delayed_col0_n <= not dqs1_delayed_col0;
dqs2_delayed_col0_n <= not dqs2_delayed_col0;
dqs3_delayed_col0_n <= not dqs3_delayed_col0;
dqs4_delayed_col0_n <= not dqs4_delayed_col0;
dqs5_delayed_col0_n <= not dqs5_delayed_col0;
dqs6_delayed_col0_n <= not dqs6_delayed_col0;
dqs7_delayed_col0_n <= not dqs7_delayed_col0;
dqs8_delayed_col0_n <= not dqs8_delayed_col0;
dqs9_delayed_col0_n <= not dqs9_delayed_col0;
dqs10_delayed_col0_n <= not dqs10_delayed_col0;
dqs11_delayed_col0_n <= not dqs11_delayed_col0;
dqs12_delayed_col0_n <= not dqs12_delayed_col0;
dqs13_delayed_col0_n <= not dqs13_delayed_col0;
-- dqsx_delayed_col1 negated signals
dqs0_delayed_col1_n <= not dqs0_delayed_col1;
dqs1_delayed_col1_n <= not dqs1_delayed_col1;
dqs2_delayed_col1_n <= not dqs2_delayed_col1;
dqs3_delayed_col1_n <= not dqs3_delayed_col1;
dqs4_delayed_col1_n <= not dqs4_delayed_col1;
dqs5_delayed_col1_n <= not dqs5_delayed_col1;
dqs6_delayed_col1_n <= not dqs6_delayed_col1;
dqs7_delayed_col1_n <= not dqs7_delayed_col1;
dqs8_delayed_col1_n <= not dqs8_delayed_col1;
dqs8_delayed_col1_n <= not dqs8_delayed_col1;
dqs9_delayed_col1_n <= not dqs9_delayed_col1;
dqs10_delayed_col1_n <= not dqs10_delayed_col1;
dqs11_delayed_col1_n <= not dqs11_delayed_col1;
dqs12_delayed_col1_n <= not dqs12_delayed_col1;
dqs13_delayed_col1_n <= not dqs13_delayed_col1;
rst_dqs_div_delayed : dqs_delay port map (
clk_in => rst_dqs_div_in,
sel_in => delay_sel,
clk_out => rst_dqs_div
);
--------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------
-- fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )
fifo_00_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_00_rd_addr
);
fifo_10_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_10_rd_addr
);
fifo_20_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_20_rd_addr
);
fifo_30_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_30_rd_addr
);
fifo_40_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_40_rd_addr
);
fifo_50_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_50_rd_addr
);
fifo_60_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_60_rd_addr
);
fifo_70_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_70_rd_addr
);
fifo_80_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_80_rd_addr
);
fifo_90_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_90_rd_addr
);
fifo_100_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_100_rd_addr
);
fifo_110_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_110_rd_addr
);
fifo_120_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_120_rd_addr
);
fifo_130_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_130_rd_addr
);
fifo_01_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_01_rd_addr
);
fifo_11_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_11_rd_addr
);
fifo_21_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_21_rd_addr
);
fifo_31_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_31_rd_addr
);
fifo_41_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_41_rd_addr
);
fifo_51_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_51_rd_addr
);
fifo_61_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_61_rd_addr
);
fifo_71_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_71_rd_addr
);
fifo_81_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_81_rd_addr
);
fifo_91_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_91_rd_addr
);
fifo_101_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_101_rd_addr
);
fifo_111_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_111_rd_addr
);
fifo_121_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_121_rd_addr
);
fifo_131_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_131_rd_addr
);
--**************************************************************************************************
-- DQS Internal Delay Circuit implemented in LUTs
--**************************************************************************************************
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay0_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in0,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(0)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay0_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in0,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(0)
);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -