data_read_56bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*********************************************************************
-- DDR 56 Bit Controller DATA PATH for LEFT RIGHT Pins

-- In the current DATA PATH logic DATA CAPTURE part was modified.
-- The below changes were made to reduce the resources in 
-- the data capture

-- in the current architecture data ( dq ) from ddr memory 
-- directly stored into the FIFO's.

-- Architectural changes :

-- Used only TWO FIFOs ( instead of FOUR FIFOs ) 
-- Used Single col ( col0 ) dqs_delayed_col signals
-- Used Gray Counters for write and read pointers of the FIFOs 

-- fbit stage is removed from ddr1_dqbit module ( in the data capture )
-- dq_clk stage was removed 
-- dqs_clk_div logic was removed
-- ddr1_transfer_done logic was removed 
-- data valid signals registering in clk90 domain was removed

-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic  
-- write enable for the FIFOs derived from rst_dqs_div signal


-- Code revised by 	: Narayana Murty.
-- Date 			      : Nov 18, 2003. 

--*********************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--

entity data_read_56bit is
port(

     clk90              : in std_logic;
     reset90_r          : in std_logic;
     ddr_dq_in          : in std_logic_vector(55 downto 0);   
     read_valid_data_1  : in std_logic;
     
     fifo_00_wr_en			: in std_logic;
     fifo_10_wr_en			: in std_logic;
     fifo_20_wr_en			: in std_logic;
     fifo_30_wr_en			: in std_logic;
     fifo_40_wr_en			: in std_logic;
     fifo_50_wr_en			: in std_logic;
     fifo_60_wr_en			: in std_logic;
   
     fifo_01_wr_en			: in std_logic;
     fifo_11_wr_en			: in std_logic;
     fifo_21_wr_en			: in std_logic;
     fifo_31_wr_en			: in std_logic;
     fifo_41_wr_en			: in std_logic;
     fifo_51_wr_en			: in std_logic;
     fifo_61_wr_en			: in std_logic;
   
     fifo_00_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_01_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_10_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_11_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_20_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_21_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_30_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_31_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_40_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_41_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_50_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_51_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_60_wr_addr    : in std_logic_vector(3 downto 0);
     fifo_61_wr_addr    : in std_logic_vector(3 downto 0);
    
 
     dqs0_delayed_col1  : in std_logic;
     dqs1_delayed_col1  : in std_logic;
     dqs2_delayed_col1  : in std_logic;
     dqs3_delayed_col1  : in std_logic;
     dqs4_delayed_col1  : in std_logic;
     dqs5_delayed_col1  : in std_logic;
     dqs6_delayed_col1  : in std_logic;
   
     dqs0_delayed_col0  : in std_logic;
     dqs1_delayed_col0  : in std_logic;
     dqs2_delayed_col0  : in std_logic;
     dqs3_delayed_col0  : in std_logic;
     dqs4_delayed_col0  : in std_logic;
     dqs5_delayed_col0  : in std_logic;
     dqs6_delayed_col0  : in std_logic;
   
     user_output_data   : out std_logic_vector(111 downto 0);
     fifo0_rd_addr_val: out std_logic_vector(3 downto 0);
     fifo1_rd_addr_val: out std_logic_vector(3 downto 0)     

     );
end data_read_56bit;


architecture arc_data_read of data_read_56bit is

attribute syn_noprune : boolean;  -- Using syn_noprune Derictive

attribute syn_preserve : boolean;  -- Using syn_noprune Derictive
-- rd_gray_cntr is a gray counter with a SYNC reset ( reset_90r) for fifo rd_addr
component rd_gray_cntr port (
			clk 				: 	in std_logic;         
			reset				:	in std_logic;
			cnt_en			        :	in std_logic; 
                        rgc_gcnt                       :       out	std_logic_vector(3 downto 0)
                        
		  );
end component; 

component FD port(
      Q        : out STD_LOGIC;
      C        : in STD_LOGIC;
      D        : in STD_LOGIC
      );
end component;

-- 16x1 Dual Port RAM Component Instansiated 

component RAM16X1D
  port (D     : in std_logic;
        WE    : in std_logic;
        WCLK  : in std_logic;
        A0    : in std_logic;
        A1    : in std_logic;
        A2    : in std_logic;
        A3    : in std_logic;
        DPRA0 : in std_logic;
        DPRA1 : in std_logic;
        DPRA2 : in std_logic;
        DPRA3 : in std_logic;
 		  SPO   : out std_logic;
        DPO   : out std_logic);

end component;


signal read_valid_data_1_r   : std_logic;
signal read_valid_data_1_r1   : std_logic;
signal read_valid_data_1_r2   : std_logic;



signal fifo00_rd_addr        : std_logic_vector(3 downto 0);
signal fifo01_rd_addr        : std_logic_vector(3 downto 0);


signal fifo00_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo01_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo10_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo11_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo20_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo21_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo30_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo31_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo40_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo41_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo50_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo51_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo60_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifo61_rd_addr_r        : std_logic_vector(3 downto 0);
signal fifop_rd_addr_r         : std_logic_vector(3 downto 0);


attribute syn_noprune of fifo00_rd_addr_r : signal is true;
attribute syn_noprune of fifo01_rd_addr_r : signal is true;
attribute syn_noprune of fifo10_rd_addr_r : signal is true;
attribute syn_noprune of fifo11_rd_addr_r : signal is true;
attribute syn_noprune of fifo20_rd_addr_r : signal is true;
attribute syn_noprune of fifo21_rd_addr_r : signal is true;
attribute syn_noprune of fifo30_rd_addr_r : signal is true;
attribute syn_noprune of fifo31_rd_addr_r : signal is true;
attribute syn_noprune of fifo40_rd_addr_r : signal is true;
attribute syn_noprune of fifo41_rd_addr_r : signal is true;
attribute syn_noprune of fifo50_rd_addr_r : signal is true;
attribute syn_noprune of fifo51_rd_addr_r : signal is true;
attribute syn_noprune of fifo60_rd_addr_r : signal is true;
attribute syn_noprune of fifo61_rd_addr_r : signal is true;
attribute syn_noprune of fifop_rd_addr_r  : signal is true;

attribute syn_preserve  of fifo00_rd_addr_r : signal is true;
attribute syn_preserve  of fifo01_rd_addr_r : signal is true;
attribute syn_preserve  of fifo10_rd_addr_r : signal is true;
attribute syn_preserve  of fifo11_rd_addr_r : signal is true;
attribute syn_preserve  of fifo20_rd_addr_r : signal is true;
attribute syn_preserve  of fifo21_rd_addr_r : signal is true;
attribute syn_preserve  of fifo30_rd_addr_r : signal is true;
attribute syn_preserve  of fifo31_rd_addr_r : signal is true;
attribute syn_preserve  of fifo40_rd_addr_r : signal is true;
attribute syn_preserve  of fifo41_rd_addr_r : signal is true;
attribute syn_preserve  of fifo50_rd_addr_r : signal is true;
attribute syn_preserve  of fifo51_rd_addr_r : signal is true;
attribute syn_preserve  of fifo60_rd_addr_r : signal is true;
attribute syn_preserve  of fifo61_rd_addr_r : signal is true;
attribute syn_preserve  of fifop_rd_addr_r  : signal is true;



signal fifo_00_data_out       : std_logic_vector(7 downto 0);
signal fifo_01_data_out       : std_logic_vector(7 downto 0);
signal fifo_10_data_out       : std_logic_vector(7 downto 0);
signal fifo_11_data_out       : std_logic_vector(7 downto 0);
signal fifo_20_data_out       : std_logic_vector(7 downto 0);
signal fifo_21_data_out       : std_logic_vector(7 downto 0);
signal fifo_30_data_out       : std_logic_vector(7 downto 0);
signal fifo_31_data_out       : std_logic_vector(7 downto 0);
signal fifo_40_data_out       : std_logic_vector(7 downto 0);
signal fifo_41_data_out       : std_logic_vector(7 downto 0);
signal fifo_50_data_out       : std_logic_vector(7 downto 0);
signal fifo_51_data_out       : std_logic_vector(7 downto 0);
signal fifo_60_data_out       : std_logic_vector(7 downto 0);
signal fifo_61_data_out       : std_logic_vector(7 downto 0);


-- reg added for timing 
signal fifo_00_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_01_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_10_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_11_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_20_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_21_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_30_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_31_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_40_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_41_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_50_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_51_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_60_data_out_r       : std_logic_vector(7 downto 0);
signal fifo_61_data_out_r       : std_logic_vector(7 downto 0);

signal first_sdr_data         : std_logic_vector(111 downto 0);

signal dqs0_delayed_col0_n	: std_logic;
signal dqs1_delayed_col0_n      : std_logic;
signal dqs2_delayed_col0_n	: std_logic;
signal dqs3_delayed_col0_n      : std_logic;
signal dqs4_delayed_col0_n	: std_logic;
signal dqs5_delayed_col0_n      : std_logic;
signal dqs6_delayed_col0_n	: std_logic;


-- Directive for synthesis   
--attribute syn_noprune of dqs0_delayed_col0_n : signal is true;
--attribute syn_noprune of dqs1_delayed_col0_n : signal is true;
--attribute syn_noprune of dqs2_delayed_col0_n : signal is true;
--attribute syn_noprune of dqs3_delayed_col0_n : signal is true;
--attribute syn_noprune of dqs4_delayed_col0_n : signal is true;
--attribute syn_noprune of dqs5_delayed_col0_n : signal is true;
--attribute syn_noprune of dqs6_delayed_col0_n : signal is true;

signal dqs0_delayed_col1_n	: std_logic;
signal dqs1_delayed_col1_n      : std_logic;
signal dqs2_delayed_col1_n	: std_logic;
signal dqs3_delayed_col1_n      : std_logic;
signal dqs4_delayed_col1_n	: std_logic;
signal dqs5_delayed_col1_n      : std_logic;
signal dqs6_delayed_col1_n	: std_logic;

-- Directive for synthesis   
--attribute syn_noprune of dqs0_delayed_col1_n : signal is true;
--attribute syn_noprune of dqs1_delayed_col1_n : signal is true;
--attribute syn_noprune of dqs2_delayed_col1_n : signal is true;
--attribute syn_noprune of dqs3_delayed_col1_n : signal is true;
--attribute syn_noprune of dqs4_delayed_col1_n : signal is true;
--attribute syn_noprune of dqs5_delayed_col1_n : signal is true;
--attribute syn_noprune of dqs6_delayed_col1_n : signal is true;


begin

dqs0_delayed_col0_n <= not dqs0_delayed_col0;
dqs1_delayed_col0_n <= not dqs1_delayed_col0;
dqs2_delayed_col0_n <= not dqs2_delayed_col0;
dqs3_delayed_col0_n <= not dqs3_delayed_col0;
dqs4_delayed_col0_n <= not dqs4_delayed_col0;
dqs5_delayed_col0_n <= not dqs5_delayed_col0;
dqs6_delayed_col0_n <= not dqs6_delayed_col0;

dqs0_delayed_col1_n <= not dqs0_delayed_col1;
dqs1_delayed_col1_n <= not dqs1_delayed_col1;
dqs2_delayed_col1_n <= not dqs2_delayed_col1;
dqs3_delayed_col1_n <= not dqs3_delayed_col1;
dqs4_delayed_col1_n <= not dqs4_delayed_col1;
dqs5_delayed_col1_n <= not dqs5_delayed_col1;
dqs6_delayed_col1_n <= not dqs6_delayed_col1;

user_output_data    <= first_sdr_data;


fifo0_rd_addr_val   <= fifo01_rd_addr;
fifo1_rd_addr_val   <= fifo00_rd_addr;


process(clk90)
begin
if clk90'event and clk90 = '1' then
 if reset90_r = '1' then
    fifo_00_data_out_r <= "00000000";
    fifo_01_data_out_r <= "00000000";
    fifo_10_data_out_r <= "00000000";
    fifo_11_data_out_r <= "00000000";
    fifo_20_data_out_r <= "00000000";
    fifo_21_data_out_r <= "00000000";
    fifo_30_data_out_r <= "00000000";
    fifo_31_data_out_r <= "00000000";
    fifo_40_data_out_r <= "00000000";
    fifo_41_data_out_r <= "00000000";
    fifo_50_data_out_r <= "00000000";
    fifo_51_data_out_r <= "00000000";
    fifo_60_data_out_r <= "00000000";