📄 data_read_controller_56bit.vhd
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);
fifo_70_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_70_rd_addr
);
fifo_80_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_80_rd_addr
);
fifo_90_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_90_rd_addr
);
fifo_100_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_100_rd_addr
);
fifo_110_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_110_rd_addr
);
fifo_120_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_120_rd_addr
);
fifo_130_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_130_rd_addr
);
fifo_01_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_01_rd_addr
);
fifo_11_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_11_rd_addr
);
fifo_21_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_21_rd_addr
);
fifo_31_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_31_rd_addr
);
fifo_41_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_41_rd_addr
);
fifo_51_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_51_rd_addr
);
fifo_61_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_61_rd_addr
);
fifo_71_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_71_rd_addr
);
fifo_81_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_81_rd_addr
);
fifo_91_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_91_rd_addr
);
fifo_101_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_101_rd_addr
);
fifo_111_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_111_rd_addr
);
fifo_121_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_121_rd_addr
);
fifo_131_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_0_1,
rgc_gcnt => fifo_131_rd_addr
);
--**************************************************************************************************
-- DQS Internal Delay Circuit implemented in LUTs
--**************************************************************************************************
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay0_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in0,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(0)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay1_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in1,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(1)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay2_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in2,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(2)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay3_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in3,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(3)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay4_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in4,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(4)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay5_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in5,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(5)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay6_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in6,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(6)
);
-- Internal Clock Delay circuit placed in the firs333t column (for falling edge data) adjacent to IOBs
dqs_delay7_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in7,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(7)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay8_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in8,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(8)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay9_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in9,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(9)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay10_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in10,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(10)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay11_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in11,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(11)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay12_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in12,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(12)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay13_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in13,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(13)
);
-------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- FIFO Write enable signal generation
-- FIFO Write enable signal generation
fifo_00_wr_en_inst: fifo_0_wr_en port map (
clk => dqs0_delayed_col0_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_0_n,
dout => fifo_00_wr_en
);
fifo_01_wr_en_inst: fifo_1_wr_en port map (
clk => dqs0_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_0_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_01_wr_en
);
fifo_10_wr_en_inst: fifo_0_wr_en port map (
clk => dqs1_delayed_col0_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_1_n,
dout => fifo_10_wr_en
);
fifo_11_wr_en_inst: fifo_1_wr_en port map (
clk => dqs1_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_1_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_11_wr_en
);
fifo_20_wr_en_inst: fifo_0_wr_en port map (
clk => dqs2_delayed_col0_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_2_n,
dout => fifo_20_wr_en
);
fifo_21_wr_en_inst: fifo_1_wr_en port map (
clk => dqs2_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_2_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_21_wr_en
);
fifo_30_wr_en_inst: fifo_0_wr_en port map (
clk => dqs3_delayed_col0_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_3_n,
dout => fifo_30_wr_en
);
fifo_31_wr_en_inst: fifo_1_wr_en port map (
clk => dqs3_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_3_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_31_wr_en
);
fifo_40_wr_en_inst: fifo_0_wr_en port map (
clk => dqs4_delayed_col0_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_4_n,
dout => fifo_40_wr_en
);
fifo_41_wr_en_inst: fifo_1_wr_en port map (
clk => dqs4_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_4_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_41_wr_en
);
fifo_50_wr_en_inst: fifo_0_wr_en port map (
clk => dqs5_delayed_col0_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_5_n,
dout => fifo_50_wr_en
);
fifo_51_wr_en_inst: fifo_1_wr_en port map (
clk => dqs5_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_5_n,
reset => reset_r,
din => rst_dqs_div,
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