📄 data_read_56bit.vhd
字号:
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(1),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit1 : RAM16X1D
port map (DPO => fifo_01_data_out(1),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(1),
DPRA0 => fifo_01_rd_addr(0),
DPRA1 => fifo_01_rd_addr(1),
DPRA2 => fifo_01_rd_addr(2),
DPRA3 => fifo_01_rd_addr(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
fifo0_bit2 : RAM16X1D
port map (DPO => fifo_00_data_out(2),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(2),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit2 : RAM16X1D
port map (DPO => fifo_01_data_out(2),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(2),
DPRA0 => fifo_01_rd_addr(0),
DPRA1 => fifo_01_rd_addr(1),
DPRA2 => fifo_01_rd_addr(2),
DPRA3 => fifo_01_rd_addr(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
fifo0_bit3 : RAM16X1D
port map (DPO => fifo_00_data_out(3),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit3 : RAM16X1D
port map (DPO => fifo_01_data_out(3),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(3),
DPRA0 => fifo_01_rd_addr(0),
DPRA1 => fifo_01_rd_addr(1),
DPRA2 => fifo_01_rd_addr(2),
DPRA3 => fifo_01_rd_addr(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
--- Nibble1 instantiation
fifo0_bit4 : RAM16X1D
port map (DPO => fifo_10_data_out(0),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(4),
DPRA0 => fifo_10_rd_addr(0),
DPRA1 => fifo_10_rd_addr(1),
DPRA2 => fifo_10_rd_addr(2),
DPRA3 => fifo_10_rd_addr(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit4 : RAM16X1D
port map (DPO => fifo_11_data_out(0),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(4),
DPRA0 => fifo_11_rd_addr(0),
DPRA1 => fifo_11_rd_addr(1),
DPRA2 => fifo_11_rd_addr(2),
DPRA3 => fifo_11_rd_addr(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
fifo0_bit5 : RAM16X1D
port map (DPO => fifo_10_data_out(1),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(5),
DPRA0 => fifo_10_rd_addr(0),
DPRA1 => fifo_10_rd_addr(1),
DPRA2 => fifo_10_rd_addr(2),
DPRA3 => fifo_10_rd_addr(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit5 : RAM16X1D
port map (DPO => fifo_11_data_out(1),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(5),
DPRA0 => fifo_11_rd_addr(0),
DPRA1 => fifo_11_rd_addr(1),
DPRA2 => fifo_11_rd_addr(2),
DPRA3 => fifo_11_rd_addr(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
fifo0_bit6 : RAM16X1D
port map (DPO => fifo_10_data_out(2),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(6),
DPRA0 => fifo_10_rd_addr(0),
DPRA1 => fifo_10_rd_addr(1),
DPRA2 => fifo_10_rd_addr(2),
DPRA3 => fifo_10_rd_addr(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit6 : RAM16X1D
port map (DPO => fifo_11_data_out(2),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(6),
DPRA0 => fifo_11_rd_addr(0),
DPRA1 => fifo_11_rd_addr(1),
DPRA2 => fifo_11_rd_addr(2),
DPRA3 => fifo_11_rd_addr(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
fifo0_bit7 : RAM16X1D
port map (DPO => fifo_10_data_out(3),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(7),
DPRA0 => fifo_10_rd_addr(0),
DPRA1 => fifo_10_rd_addr(1),
DPRA2 => fifo_10_rd_addr(2),
DPRA3 => fifo_10_rd_addr(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit7 : RAM16X1D
port map (DPO => fifo_11_data_out(3),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(7),
DPRA0 => fifo_11_rd_addr(0),
DPRA1 => fifo_11_rd_addr(1),
DPRA2 => fifo_11_rd_addr(2),
DPRA3 => fifo_11_rd_addr(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
--- Nibble2 instantiation
fifo0_bit8 : RAM16X1D
port map (DPO => fifo_20_data_out(0),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(8),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col0,
WE => fifo_20_wr_en );
fifo1_bit8 : RAM16X1D
port map (DPO => fifo_21_data_out(0),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(8),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit9 : RAM16X1D
port map (DPO => fifo_20_data_out(1),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(9),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col0,
WE => fifo_20_wr_en );
fifo1_bit9 : RAM16X1D
port map (DPO => fifo_21_data_out(1),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(9),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit10 : RAM16X1D
port map (DPO => fifo_20_data_out(2),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(10),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col0,
WE => fifo_20_wr_en );
fifo1_bit10 : RAM16X1D
port map (DPO => fifo_21_data_out(2),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(10),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit11 : RAM16X1D
port map (DPO => fifo_20_data_out(3),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(11),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col0,
WE => fifo_20_wr_en );
fifo1_bit11 : RAM16X1D
port map (DPO => fifo_21_data_out(3),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(11),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
--- Nibble3 instantiation
fifo0_bit12 : RAM16X1D
port map (DPO => fifo_30_data_out(0),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(12),
DPRA0 => fifo_30_rd_addr(0),
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -