data_path_iobs_8bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*********************************************************************
-- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins

-- In the current DATA PATH logic DATA CAPTURE part was modified.
-- The below changes were made to reduce the resources in 
-- the data capture

-- in the current architecture data ( dq ) from ddr memory 
-- directly stored into the FIFO's.

-- Architectural changes :

-- Used only TWO FIFOs ( instead of FOUR FIFOs ) 
-- Used Single col ( col0 ) dqs_delayed_col signals
-- Used Gray Counters for write and read pointers of the FIFOs 

-- fbit stage is removed from ddr1_dqbit module ( in the data capture )
-- dq_clk stage was removed 
-- dqs_clk_div logic was removed
-- ddr1_transfer_done logic was removed 
-- data valid signals registering in clk90 domain was removed

-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic  
-- write enable for the FIFOs derived from rst_dqs_div signal


-- Code revised by 	: Narayana Murty.
-- Date 			      : Nov 18, 2003. 

--*********************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
use work.parameter_8bit.all;

entity   data_path_iobs_8bit  is
port(
    clk               : in std_logic;
    clk90             : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
    reset90_r         : in std_logic;
    dqs_reset         : in std_logic;
    dqs_enable        : in std_logic;
    ddr_dqs           : inout std_logic;
    ddr_dq            : inout std_logic_vector(7 downto 0);
    write_data_falling: in std_logic_vector(7 downto 0);
    write_data_rising : in std_logic_vector(7 downto 0);
    write_en_val      : in std_logic;
    data_mask_f       : in std_logic_vector(0 downto 0);
    data_mask_r       : in std_logic_vector(0 downto 0);
    dqs_int_delay_in0 : out std_logic;
    ddr_dq_val        : out std_logic_vector(7 downto 0);
    ddr_dm            : out std_logic
);
end   data_path_iobs_8bit;  


architecture arc_data_path_iobs_8bit of data_path_iobs_8bit is


attribute syn_keep : boolean;  -- Using Syn_Keep Derictive


component ddr_dqs_iob
port(
     clk            : in std_logic;
     clk180         : in std_logic;
     ddr_dqs_reset  : in std_logic;
     ddr_dqs_enable : in std_logic;
     ddr_dqs        : inout std_logic;
     dqs            : out std_logic
     );
end component;

component ddr_dq_iob  
port (
      ddr_dq_inout       : inout std_logic; --Bi-directional SDRAM data bus
      write_data_falling : in std_logic;    --Transmit data, output on falling edge
      write_data_rising  : in std_logic;    --Transmit data, output on rising edge
      read_data_in       : out std_logic;   -- Received data
      clk90              : in std_logic;    --Clock 90
      clk270             : in std_logic;
      write_en_val       : in std_logic;    --Transmit enable
      reset              : in std_logic); 

end component;

component	ddr1_dm_8bit 
port (                                                
      ddr_dm       : out std_logic;
      mask_falling : in std_logic_vector(0 downto 0); 
      mask_rising  : in std_logic_vector(0 downto 0); 
      clk90        : in std_logic;    
      clk270       : in std_logic                     
      );                                              
end component;                                        

--SYN_REMOVECOMMENT signal clk270       : std_logic;
--SYN_REMOVECOMMENT signal clk180       : std_logic;
signal ddr_dq_in    : std_logic_vector( 7 downto 0);
--SYN_REMOVECOMMENT attribute syn_keep of clk180 : signal is true; 
--SYN_REMOVECOMMENT attribute syn_keep of clk270 : signal is true; 

begin

--SYN_REMOVECOMMENT clk270  <=  not clk90;
--SYN_REMOVECOMMENT clk180  <=  not clk;

ddr_dq_val <= ddr_dq_in;

ddr1_dm0	:	ddr1_dm_8bit	port	map	( 
                             ddr_dm       => ddr_dm,
                             mask_falling => data_mask_f,
                             mask_rising  => data_mask_r,
                             clk90        => clk90,
                             clk270       => clk270
                            );


--***********************************************************************
--    Read Data Capture Module Instantiations
--***********************************************************************
-- DQS IOB instantiations
--***********************************************************************

 ddr_dqs_iob0 : ddr_dqs_iob port map (
                              clk            => clk,
                              clk180         => clk180,
                              ddr_dqs_reset  => dqs_reset,
                              ddr_dqs_enable => dqs_enable,
                              ddr_dqs        => ddr_dqs,
                              dqs            => dqs_int_delay_in0
					);
                             


--******************************************************************************************************************************
-- DDR Data bit instantiations (72-bits)
--******************************************************************************************************************************            
   
ddr_dq_iob0 : ddr_dq_iob  port map(
      							ddr_dq_inout       => ddr_dq(0),
      							write_data_falling => write_data_falling(0),
      							write_data_rising  => write_data_rising(0),
      							read_data_in       => ddr_dq_in(0),
      							clk90              => clk90,
      							clk270             => clk270,
      							write_en_val       => write_en_val,
      							reset              => reset90_r
						    	);


ddr_dq_iob1 : ddr_dq_iob  port map(
      							ddr_dq_inout       => ddr_dq(1),
      							write_data_falling => write_data_falling(1),
      							write_data_rising  => write_data_rising(1),
      							read_data_in       => ddr_dq_in(1),
      							clk90              => clk90,
      							clk270             => clk270,
      							write_en_val       => write_en_val,
      							reset              => reset90_r
						    	);

ddr_dq_iob2 : ddr_dq_iob  port map(
      							ddr_dq_inout       => ddr_dq(2),
      							write_data_falling => write_data_falling(2),
      							write_data_rising  => write_data_rising(2),
      							read_data_in       => ddr_dq_in(2),
      							clk90              => clk90,
      							clk270             => clk270,
      							write_en_val       => write_en_val,
      							reset              => reset90_r
						    	);

ddr_dq_iob3 : ddr_dq_iob  port map(
      							ddr_dq_inout       => ddr_dq(3),
      							write_data_falling => write_data_falling(3),
      							write_data_rising  => write_data_rising(3),
      							read_data_in       => ddr_dq_in(3),
      							clk90              => clk90,
      							clk270             => clk270,
      							write_en_val       => write_en_val,
      							reset              => reset90_r
						    	);

ddr_dq_iob4 : ddr_dq_iob  port map(
      							ddr_dq_inout       => ddr_dq(4),
      							write_data_falling => write_data_falling(4),
      							write_data_rising  => write_data_rising(4),
      							read_data_in       => ddr_dq_in(4),
      							clk90              => clk90,
      							clk270             => clk270,
      							write_en_val       => write_en_val,
      							reset              => reset90_r
						    	);

ddr_dq_iob5 : ddr_dq_iob  port map(
      							ddr_dq_inout       => ddr_dq(5),
      							write_data_falling => write_data_falling(5),
      							write_data_rising  => write_data_rising(5),
      							read_data_in       => ddr_dq_in(5),
      							clk90              => clk90,
      							clk270             => clk270,
      							write_en_val       => write_en_val,
      							reset              => reset90_r
						    	);

ddr_dq_iob6 : ddr_dq_iob  port map(
      							ddr_dq_inout       => ddr_dq(6),
      							write_data_falling => write_data_falling(6),
      							write_data_rising  => write_data_rising(6),
      							read_data_in       => ddr_dq_in(6),
      							clk90              => clk90,
      							clk270             => clk270,
      							write_en_val       => write_en_val,
      							reset              => reset90_r
						    	);

ddr_dq_iob7 : ddr_dq_iob  port map(
      							ddr_dq_inout       => ddr_dq(7),
      							write_data_falling => write_data_falling(7),
      							write_data_rising  => write_data_rising(7),
      							read_data_in       => ddr_dq_in(7),
      							clk90              => clk90,
      							clk270             => clk270,
      							write_en_val       => write_en_val,
      							reset              => reset90_r
						    	);


end arc_data_path_iobs_8bit;