data_read_controller_64bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

	                             );

                
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay3_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in3,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(3)                               
	                             );

-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay4_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in4,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(4)                               
	                             );

-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay5_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in5,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(5)                               
	                             );


	                    
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay6_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in6,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(6)                               
	                             );
	                    
-- Internal Clock Delay circuit placed in the firs333t column (for falling edge data) adjacent to IOBs                               
dqs_delay7_col0 : dqs_delay port map (                                                                          
	                              clk_in   => dqs_int_delay_in7,
	                              sel_in   => delay_sel,                                
	                              clk_out  => dqs_delayed_col0(7)
	                             );

-------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------

-- FIFO Write enable signal generation

-- FIFO Write enable signal generation

fifo_00_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs0_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_0_n,
						dout		=> fifo_00_wr_en
				   	   );

fifo_01_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs0_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_01_wr_en
				          );

fifo_10_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs1_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_1_n,
						dout		=> fifo_10_wr_en
				   	   );

fifo_11_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs1_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_1_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_11_wr_en
				          );


fifo_20_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs2_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_2_n,
						dout		=> fifo_20_wr_en
				   	   );

fifo_21_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs2_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_2_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_21_wr_en
				          );

fifo_30_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs3_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_3_n,
						dout		=> fifo_30_wr_en
				   	   );

fifo_31_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs3_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_3_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_31_wr_en
				          );

fifo_40_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs4_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_4_n,
						dout		=> fifo_40_wr_en
				   	   );

fifo_41_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs4_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_4_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_41_wr_en
				          );

fifo_50_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs5_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_5_n,
						dout		=> fifo_50_wr_en
				   	   );

fifo_51_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs5_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_5_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_51_wr_en
				          );

fifo_60_wr_en_inst: fifo_0_wr_en port map (

						clk 		=> dqs6_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_6_n,
						dout		=> fifo_60_wr_en
				   	   );

fifo_61_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs6_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_6_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_61_wr_en
				          );

fifo_70_wr_en_inst: fifo_0_wr_en port map (
						clk 		=> dqs7_delayed_col0_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						rst_dqs_delay_n => rst_dqs_delay_7_n,
						dout		=> fifo_70_wr_en
				   	   );

fifo_71_wr_en_inst: fifo_1_wr_en port map (
						clk		=> dqs7_delayed_col0,
						rst_dqs_delay_n => rst_dqs_delay_7_n,
						reset		=> reset_r,
						din		=> rst_dqs_div,
						dout		=> fifo_71_wr_en
				          );
-------------------------------------------------------------------------------------------------
-- write pointer gray counter instances 

fifo_00_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs0_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_00_wr_en,
							wgc_gcnt		=>	fifo_00_wr_addr
						);

fifo_01_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs0_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_01_wr_en,
							wgc_gcnt		=>	fifo_01_wr_addr
						);


fifo_10_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs1_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_10_wr_en,
							wgc_gcnt		=>	fifo_10_wr_addr
						);


fifo_11_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs1_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_11_wr_en,
							wgc_gcnt		=>	fifo_11_wr_addr
						);

fifo_20_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs2_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_20_wr_en,
							wgc_gcnt		=>	fifo_20_wr_addr
						);


fifo_21_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs2_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_21_wr_en,
							wgc_gcnt		=>	fifo_21_wr_addr
						);

fifo_30_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs3_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_30_wr_en,
							wgc_gcnt		=>	fifo_30_wr_addr
						);


fifo_31_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs3_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_31_wr_en,
							wgc_gcnt		=>	fifo_31_wr_addr
						);


fifo_40_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs4_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_40_wr_en,
							wgc_gcnt		=>	fifo_40_wr_addr
						);


fifo_41_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs4_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_41_wr_en,
							wgc_gcnt		=>	fifo_41_wr_addr
						);

fifo_50_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs5_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_50_wr_en,
							wgc_gcnt		=>	fifo_50_wr_addr
						);


fifo_51_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs5_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_51_wr_en,
							wgc_gcnt		=>	fifo_51_wr_addr
						);


fifo_60_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs6_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_60_wr_en,
							wgc_gcnt		=>	fifo_60_wr_addr
						);


fifo_61_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs6_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_61_wr_en,
							wgc_gcnt		=>	fifo_61_wr_addr
						);


fifo_70_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs7_delayed_col0,
							reset		=>	reset_r,
							cnt_en	=>	fifo_70_wr_en,
							wgc_gcnt		=>	fifo_70_wr_addr
						);


fifo_71_wr_addr_inst : wr_gray_cntr port map (
							clk 		=>	dqs7_delayed_col0_n,
							reset		=>	reset_r,
							cnt_en	=>	fifo_71_wr_en,
							wgc_gcnt		=>	fifo_71_wr_addr
						);
end   arc_data_read_controller_64bit;