📄 iobs.vhd
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library ieee;
use ieee.std_logic_1164.all;
use work.parameter_64bit.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity iobs is
port(
SYS_CLK : in std_logic;
SYS_CLKb : in std_logic;
clk : in std_logic;
clk90 : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
ddr_rasb_cntrl : in std_logic;
ddr_casb_cntrl : in std_logic;
ddr_web_cntrl : in std_logic;
ddr_cke_cntrl : in std_logic;
ddr_csb_cntrl : in std_logic;
ddr_address_cntrl : in std_logic_vector(12 downto 0);
ddr_ba_cntrl : in std_logic_vector(1 downto 0);
rst_dqs_div_int : in std_logic;
dqs_reset : in std_logic;
dqs_enable : in std_logic;
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dq : inout std_logic_vector(63 downto 0);
write_data_falling: in std_logic_vector(63 downto 0);
write_data_rising : in std_logic_vector(63 downto 0);
write_en_val : in std_logic;
reset90_r : in std_logic;
data_mask_f : in std_logic_vector(7 downto 0);
data_mask_r : in std_logic_vector(7 downto 0);
sys_clk_ibuf : out std_logic;
ddr1_clk0 : out std_logic;
ddr1_clk0b : out std_logic;
ddr1_clk1 : out std_logic;
ddr1_clk1b : out std_logic;
ddr1_clk2 : out std_logic;
ddr1_clk2b : out std_logic;
ddr1_clk3 : out std_logic;
ddr1_clk3b : out std_logic;
ddr_rasb : out std_logic;
ddr_casb : out std_logic;
ddr_web : out std_logic;
ddr_ba : out std_logic_vector(1 downto 0);
ddr_address : out std_logic_vector(12 downto 0);
ddr_cke : out std_logic;
ddr_csb : out std_logic;
rst_dqs_div : out std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
dqs_int_delay_in0 : out std_logic;
dqs_int_delay_in1 : out std_logic;
dqs_int_delay_in2 : out std_logic;
dqs_int_delay_in3 : out std_logic;
dqs_int_delay_in4 : out std_logic;
dqs_int_delay_in5 : out std_logic;
dqs_int_delay_in6 : out std_logic;
dqs_int_delay_in7 : out std_logic;
dq : out std_logic_vector(63 downto 0);
ddr_dm : out std_logic_vector(7 downto 0)
);
end iobs;
architecture arc_iobs of iobs is
component infrastructure_iobs
port(
SYS_CLK : in std_logic;
SYS_CLKb : in std_logic;
clk0 : in std_logic;
clk90 : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
sys_clk_ibuf : out std_logic;
ddr1_clk0 : out std_logic;
ddr1_clk0b : out std_logic;
ddr1_clk1 : out std_logic;
ddr1_clk1b : out std_logic;
ddr1_clk2 : out std_logic;
ddr1_clk2b : out std_logic;
ddr1_clk3 : out std_logic;
ddr1_clk3b : out std_logic
);
end component;
component controller_iobs
port(
clk0 : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
ddr_rasb_cntrl : in std_logic;
ddr_casb_cntrl : in std_logic;
ddr_web_cntrl : in std_logic;
ddr_cke_cntrl : in std_logic;
ddr_csb_cntrl : in std_logic;
ddr_address_cntrl: in std_logic_vector(12 downto 0);
ddr_ba_cntrl : in std_logic_vector(1 downto 0);
rst_dqs_div_int : in std_logic;
ddr_rasb : out std_logic;
ddr_casb : out std_logic;
ddr_web : out std_logic;
ddr_ba : out std_logic_vector(1 downto 0);
ddr_address : out std_logic_vector(12 downto 0);
ddr_cke : out std_logic;
ddr_csb : out std_logic;
rst_dqs_div : out std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic
);
end component;
component data_path_iobs_64bit
port(
clk : in std_logic;
clk90 : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
reset90_r : in std_logic;
dqs_reset : in std_logic;
dqs_enable : in std_logic;
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dq : inout std_logic_vector(63 downto 0);
write_data_falling: in std_logic_vector(63 downto 0);
write_data_rising : in std_logic_vector(63 downto 0);
write_en_val : in std_logic;
data_mask_f : in std_logic_vector(7 downto 0);
data_mask_r : in std_logic_vector(7 downto 0);
dqs_int_delay_in0 : out std_logic;
dqs_int_delay_in1 : out std_logic;
dqs_int_delay_in2 : out std_logic;
dqs_int_delay_in3 : out std_logic;
dqs_int_delay_in4 : out std_logic;
dqs_int_delay_in5 : out std_logic;
dqs_int_delay_in6 : out std_logic;
dqs_int_delay_in7 : out std_logic;
ddr_dq_val : out std_logic_vector(63 downto 0);
ddr_dm : out std_logic_vector(7 downto 0)
);
end component;
begin
infrastructure_iobs0 : infrastructure_iobs port map (
SYS_CLK => SYS_CLK,
SYS_CLKb => SYS_CLKb,
clk0 => clk,
clk90 => clk90,
--XST_REMOVECOMMENT clk180 => clk180,
--XST_REMOVECOMMENT clk270 => clk270,
sys_clk_ibuf => sys_clk_ibuf,
ddr1_clk0 => ddr1_clk0,
ddr1_clk0b => ddr1_clk0b,
ddr1_clk1 => ddr1_clk1,
ddr1_clk1b => ddr1_clk1b,
ddr1_clk2 => ddr1_clk2,
ddr1_clk2b => ddr1_clk2b,
ddr1_clk3 => ddr1_clk3,
ddr1_clk3b => ddr1_clk3b
);
controller_iobs0 : controller_iobs port map (
clk0 => clk,
--XST_REMOVECOMMENT clk180 => clk180,
ddr_rasb_cntrl => ddr_rasb_cntrl,
ddr_casb_cntrl => ddr_casb_cntrl,
ddr_web_cntrl => ddr_web_cntrl,
ddr_cke_cntrl => ddr_cke_cntrl,
ddr_csb_cntrl => ddr_csb_cntrl,
ddr_address_cntrl => ddr_address_cntrl(12 downto 0),
ddr_ba_cntrl => ddr_ba_cntrl(1 downto 0),
rst_dqs_div_int => rst_dqs_div_int,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_web => ddr_web,
ddr_ba => ddr_ba(1 downto 0),
ddr_address => ddr_address(12 downto 0),
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
rst_dqs_div => rst_dqs_div,
rst_dqs_div_in => rst_dqs_div_in,
rst_dqs_div_out => rst_dqs_div_out
);
datapath_iobs0 : data_path_iobs_64bit port map (
clk => clk,
clk90 => clk90,
--XST_REMOVECOMMENT clk180 => clk180,
--XST_REMOVECOMMENT clk270 => clk270,
reset90_r => reset90_r,
dqs_reset => dqs_reset,
dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(7 downto 0),
ddr_dq => ddr_dq(63 downto 0),
write_data_falling => write_data_falling(63 downto 0),
write_data_rising => write_data_rising(63 downto 0),
write_en_val => write_en_val,
data_mask_f => data_mask_f(7 downto 0),
data_mask_r => data_mask_r(7 downto 0),
dqs_int_delay_in0 => dqs_int_delay_in0,
dqs_int_delay_in1 => dqs_int_delay_in1,
dqs_int_delay_in2 => dqs_int_delay_in2,
dqs_int_delay_in3 => dqs_int_delay_in3,
dqs_int_delay_in4 => dqs_int_delay_in4,
dqs_int_delay_in5 => dqs_int_delay_in5,
dqs_int_delay_in6 => dqs_int_delay_in6,
dqs_int_delay_in7 => dqs_int_delay_in7,
ddr_dq_val => dq(63 downto 0),
ddr_dm => ddr_dm(7 downto 0)
);
end arc_iobs;
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