📄 data_read_48bit.vhd
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WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit26 : RAM16X1D
port map (DPO => fifo_31_data_out(2),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(26),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit27 : RAM16X1D
port map (DPO => fifo_30_data_out(3),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(27),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit27 : RAM16X1D
port map (DPO => fifo_31_data_out(3),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(27),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit28 : RAM16X1D
port map (DPO => fifo_30_data_out(4),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(28),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit28 : RAM16X1D
port map (DPO => fifo_31_data_out(4),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(28),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit29 : RAM16X1D
port map (DPO => fifo_30_data_out(5),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(29),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit29 : RAM16X1D
port map (DPO => fifo_31_data_out(5),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(29),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit30 : RAM16X1D
port map (DPO => fifo_30_data_out(6),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(30),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit30 : RAM16X1D
port map (DPO => fifo_31_data_out(6),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(30),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit31 : RAM16X1D
port map (DPO => fifo_30_data_out(7),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(31),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit31 : RAM16X1D
port map (DPO => fifo_31_data_out(7),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(31),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
--- Byte4 instantiation
fifo0_bit32 : RAM16X1D
port map (DPO => fifo_40_data_out(0),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(32),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col1,
WE => fifo_40_wr_en );
fifo1_bit32 : RAM16X1D
port map (DPO => fifo_41_data_out(0),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(32),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
fifo0_bit33 : RAM16X1D
port map (DPO => fifo_40_data_out(1),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(33),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col1,
WE => fifo_40_wr_en );
fifo1_bit33 : RAM16X1D
port map (DPO => fifo_41_data_out(1),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(33),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
fifo0_bit34 : RAM16X1D
port map (DPO => fifo_40_data_out(2),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(34),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col1,
WE => fifo_40_wr_en );
fifo1_bit34 : RAM16X1D
port map (DPO => fifo_41_data_out(2),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(34),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
fifo0_bit35 : RAM16X1D
port map (DPO => fifo_40_data_out(3),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(35),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col1,
WE => fifo_40_wr_en );
fifo1_bit35 : RAM16X1D
port map (DPO => fifo_41_data_out(3),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(35),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
fifo0_bit36 : RAM16X1D
port map (DPO => fifo_40_data_out(4),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(36),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col1,
WE => fifo_40_wr_en );
fifo1_bit36 : RAM16X1D
port map (DPO => fifo_41_data_out(4),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(36),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
fifo0_bit37 : RAM16X1D
port map (DPO => fifo_40_data_out(5),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(37),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
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