📄 data_read_controller_48bit.vhd
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fifo_00_wr_addr_3d <= fifo_00_wr_addr_2d;
fifo_01_wr_addr_3d <= fifo_01_wr_addr_2d;
end if;
end if;
end process;
-- user data valid output signal from data path.
fifo_00_empty <= '1' when (fifo0_rd_addr(3 downto 0) = fifo_00_wr_addr_3d(3 downto 0)) else '0';
fifo_01_empty <= '1' when (fifo1_rd_addr(3 downto 0) = fifo_01_wr_addr_3d(3 downto 0)) else '0';
read_valid_data_0_1 <= ( (not fifo_00_empty) and (not fifo_01_empty) );
read_valid_data_1_val <= (read_valid_data_0_1);
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
u_data_val <= '0';
read_valid_data_r <= '0';
read_valid_data_r1 <= '0';
else
read_valid_data_r <= read_valid_data_0_1;
read_valid_data_r1 <= read_valid_data_r;
u_data_val <= read_valid_data_r1;
end if;
end if;
end process;
--- Assignments done by MURTHY
-- here vector component is assigned to a scalar signal
-- it was done because the delay_dqs signals were used
dqs0_delayed_col0 <= dqs_delayed_col0(0);
dqs1_delayed_col0 <= dqs_delayed_col0(1);
dqs2_delayed_col0 <= dqs_delayed_col0(2);
dqs3_delayed_col0 <= dqs_delayed_col0(3);
dqs4_delayed_col0 <= dqs_delayed_col0(4);
dqs5_delayed_col0 <= dqs_delayed_col0(5);
---- Added on JAN28 ----
dqs0_delayed_col1 <= dqs_delayed_col1(0);
dqs1_delayed_col1 <= dqs_delayed_col1(1);
dqs2_delayed_col1 <= dqs_delayed_col1(2);
dqs3_delayed_col1 <= dqs_delayed_col1(3);
dqs4_delayed_col1 <= dqs_delayed_col1(4);
dqs5_delayed_col1 <= dqs_delayed_col1(5);
-- dqsx_delayed_col0 negated signals
rst_dqs_div_delayed1 : dqs_delay port map (
clk_in => rst_dqs_div_in,
sel_in => delay_sel,
clk_out => rst_dqs_div
);
--------------------------------------------------------------------------------------------------------------------------------------------------
--**************************************************************************************************
-- DQS Internal Delay Circuit implemented in LUTs
--**************************************************************************************************
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay0_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in0,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(0)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay0_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in0,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(0)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay1_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in1,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(1)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay1_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in1,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(1)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay2_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in2,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(2)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay2_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in2,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(2)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay3_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in3,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(3)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay3_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in3,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(3)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay4_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in4,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(4)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay4_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in4,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(4)
);
-- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay5_col0 : dqs_delay port map (
clk_in => dqs_int_delay_in5,
sel_in => delay_sel,
clk_out => dqs_delayed_col0(5)
);
-- Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay5_col1 : dqs_delay port map (
clk_in => dqs_int_delay_in5,
sel_in => delay_sel,
clk_out => dqs_delayed_col1(5)
);
-------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
fifo_00_wr_en_inst: fifo_0_wr_en port map (
clk => dqs0_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_0_n,
dout => fifo_00_wr_en
);
fifo_01_wr_en_inst: fifo_1_wr_en port map (
clk => dqs0_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_0_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_01_wr_en
);
fifo_10_wr_en_inst: fifo_0_wr_en port map (
clk => dqs1_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_1_n,
dout => fifo_10_wr_en
);
fifo_11_wr_en_inst: fifo_1_wr_en port map (
clk => dqs1_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_1_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_11_wr_en
);
fifo_20_wr_en_inst: fifo_0_wr_en port map (
clk => dqs2_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_2_n,
dout => fifo_20_wr_en
);
fifo_21_wr_en_inst: fifo_1_wr_en port map (
clk => dqs2_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_2_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_21_wr_en
);
fifo_30_wr_en_inst: fifo_0_wr_en port map (
clk => dqs3_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_3_n,
dout => fifo_30_wr_en
);
fifo_31_wr_en_inst: fifo_1_wr_en port map (
clk => dqs3_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_3_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_31_wr_en
);
fifo_40_wr_en_inst: fifo_0_wr_en port map (
clk => dqs4_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_4_n,
dout => fifo_40_wr_en
);
fifo_41_wr_en_inst: fifo_1_wr_en port map (
clk => dqs4_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_4_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_41_wr_en
);
fifo_50_wr_en_inst: fifo_0_wr_en port map (
clk => dqs5_delayed_col1_n,
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_5_n,
dout => fifo_50_wr_en
);
fifo_51_wr_en_inst: fifo_1_wr_en port map (
clk => dqs5_delayed_col0,
rst_dqs_delay_n => rst_dqs_delay_5_n,
reset => reset_r,
din => rst_dqs_div,
dout => fifo_51_wr_en
);
-------------------------------------------------------------------------------------------------
-- write pointer gray counter instances
fifo_00_wr_addr_inst : wr_gray_cntr port map (
clk => dqs0_delayed_col1,
reset => reset_r,
cnt_en => fifo_00_wr_en,
wgc_gcnt => fifo_00_wr_addr
);
fifo_01_wr_addr_inst : wr_gray_cntr port map (
clk => dqs0_delayed_col0_n,
reset => reset_r,
cnt_en => fifo_01_wr_en,
wgc_gcnt => fifo_01_wr_addr
);
fifo_10_wr_addr_inst : wr_gray_cntr port map (
clk => dqs1_delayed_col1,
reset => reset_r,
cnt_en => fifo_10_wr_en,
wgc_gcnt => fifo_10_wr_addr
);
fifo_11_wr_addr_inst : wr_gray_cntr port map (
clk => dqs1_delayed_col0_n,
reset => reset_r,
cnt_en => fifo_11_wr_en,
wgc_gcnt => fifo_11_wr_addr
);
fifo_20_wr_addr_inst : wr_gray_cntr port map (
clk => dqs2_delayed_col1,
reset => reset_r,
cnt_en => fifo_20_wr_en,
wgc_gcnt => fifo_20_wr_addr
);
fifo_21_wr_addr_inst : wr_gray_cntr port map (
clk => dqs2_delayed_col0_n,
reset => reset_r,
cnt_en => fifo_21_wr_en,
wgc_gcnt => fifo_21_wr_addr
);
fifo_30_wr_addr_inst : wr_gray_cntr port map (
clk => dqs3_delayed_col1,
reset => reset_r,
cnt_en => fifo_30_wr_en,
wgc_gcnt => fifo_30_wr_addr
);
fifo_31_wr_addr_inst : wr_gray_cntr port map (
clk => dqs3_delayed_col0_n,
reset => reset_r,
cnt_en => fifo_31_wr_en,
wgc_gcnt => fifo_31_wr_addr
);
fifo_40_wr_addr_inst : wr_gray_cntr port map (
clk => dqs4_delayed_col1,
reset => reset_r,
cnt_en => fifo_40_wr_en,
wgc_gcnt => fifo_40_wr_addr
);
fifo_41_wr_addr_inst : wr_gray_cntr port map (
clk => dqs4_delayed_col0_n,
reset => reset_r,
cnt_en => fifo_41_wr_en,
wgc_gcnt => fifo_41_wr_addr
);
fifo_50_wr_addr_inst : wr_gray_cntr port map (
clk => dqs5_delayed_col1,
reset => reset_r,
cnt_en => fifo_50_wr_en,
wgc_gcnt => fifo_50_wr_addr
);
fifo_51_wr_addr_inst : wr_gray_cntr port map (
clk => dqs5_delayed_col0_n,
reset => reset_r,
cnt_en => fifo_51_wr_en,
wgc_gcnt => fifo_51_wr_addr
);
end arc_data_read_controller;
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