📄 data_read_48bit.vhd
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DPRA3 => fifo_60_rd_addr(3),
WCLK => dqs6_delayed_col0,
WE => fifo_60_wr_en );
fifo1_bit24 : RAM16X1D
port map (DPO => fifo_61_data_out(0),
A0 => fifo_61_wr_addr(0),
A1 => fifo_61_wr_addr(1),
A2 => fifo_61_wr_addr(2),
A3 => fifo_61_wr_addr(3),
D => ddr_dq_in(24),
DPRA0 => fifo_61_rd_addr(0),
DPRA1 => fifo_61_rd_addr(1),
DPRA2 => fifo_61_rd_addr(2),
DPRA3 => fifo_61_rd_addr(3),
WCLK => dqs6_delayed_col0_n,
WE => fifo_61_wr_en );
fifo0_bit25 : RAM16X1D
port map (DPO => fifo_60_data_out(1),
A0 => fifo_60_wr_addr(0),
A1 => fifo_60_wr_addr(1),
A2 => fifo_60_wr_addr(2),
A3 => fifo_60_wr_addr(3),
D => ddr_dq_in(25),
DPRA0 => fifo_60_rd_addr(0),
DPRA1 => fifo_60_rd_addr(1),
DPRA2 => fifo_60_rd_addr(2),
DPRA3 => fifo_60_rd_addr(3),
WCLK => dqs6_delayed_col0,
WE => fifo_60_wr_en );
fifo1_bit25 : RAM16X1D
port map (DPO => fifo_61_data_out(1),
A0 => fifo_61_wr_addr(0),
A1 => fifo_61_wr_addr(1),
A2 => fifo_61_wr_addr(2),
A3 => fifo_61_wr_addr(3),
D => ddr_dq_in(25),
DPRA0 => fifo_61_rd_addr(0),
DPRA1 => fifo_61_rd_addr(1),
DPRA2 => fifo_61_rd_addr(2),
DPRA3 => fifo_61_rd_addr(3),
WCLK => dqs6_delayed_col0_n,
WE => fifo_61_wr_en );
fifo0_bit26 : RAM16X1D
port map (DPO => fifo_60_data_out(2),
A0 => fifo_60_wr_addr(0),
A1 => fifo_60_wr_addr(1),
A2 => fifo_60_wr_addr(2),
A3 => fifo_60_wr_addr(3),
D => ddr_dq_in(26),
DPRA0 => fifo_60_rd_addr(0),
DPRA1 => fifo_60_rd_addr(1),
DPRA2 => fifo_60_rd_addr(2),
DPRA3 => fifo_60_rd_addr(3),
WCLK => dqs6_delayed_col0,
WE => fifo_60_wr_en );
fifo1_bit26 : RAM16X1D
port map (DPO => fifo_61_data_out(2),
A0 => fifo_61_wr_addr(0),
A1 => fifo_61_wr_addr(1),
A2 => fifo_61_wr_addr(2),
A3 => fifo_61_wr_addr(3),
D => ddr_dq_in(26),
DPRA0 => fifo_61_rd_addr(0),
DPRA1 => fifo_61_rd_addr(1),
DPRA2 => fifo_61_rd_addr(2),
DPRA3 => fifo_61_rd_addr(3),
WCLK => dqs6_delayed_col0_n,
WE => fifo_61_wr_en );
fifo0_bit27 : RAM16X1D
port map (DPO => fifo_60_data_out(3),
A0 => fifo_60_wr_addr(0),
A1 => fifo_60_wr_addr(1),
A2 => fifo_60_wr_addr(2),
A3 => fifo_60_wr_addr(3),
D => ddr_dq_in(27),
DPRA0 => fifo_60_rd_addr(0),
DPRA1 => fifo_60_rd_addr(1),
DPRA2 => fifo_60_rd_addr(2),
DPRA3 => fifo_60_rd_addr(3),
WCLK => dqs6_delayed_col0,
WE => fifo_60_wr_en );
fifo1_bit27 : RAM16X1D
port map (DPO => fifo_61_data_out(3),
A0 => fifo_61_wr_addr(0),
A1 => fifo_61_wr_addr(1),
A2 => fifo_61_wr_addr(2),
A3 => fifo_61_wr_addr(3),
D => ddr_dq_in(27),
DPRA0 => fifo_61_rd_addr(0),
DPRA1 => fifo_61_rd_addr(1),
DPRA2 => fifo_61_rd_addr(2),
DPRA3 => fifo_61_rd_addr(3),
WCLK => dqs6_delayed_col0_n,
WE => fifo_61_wr_en );
--- Nibble7 instantiation
fifo0_bit28 : RAM16X1D
port map (DPO => fifo_70_data_out(0),
A0 => fifo_70_wr_addr(0),
A1 => fifo_70_wr_addr(1),
A2 => fifo_70_wr_addr(2),
A3 => fifo_70_wr_addr(3),
D => ddr_dq_in(28),
DPRA0 => fifo_70_rd_addr(0),
DPRA1 => fifo_70_rd_addr(1),
DPRA2 => fifo_70_rd_addr(2),
DPRA3 => fifo_70_rd_addr(3),
WCLK => dqs7_delayed_col0,
WE => fifo_70_wr_en );
fifo1_bit28 : RAM16X1D
port map (DPO => fifo_71_data_out(0),
A0 => fifo_71_wr_addr(0),
A1 => fifo_71_wr_addr(1),
A2 => fifo_71_wr_addr(2),
A3 => fifo_71_wr_addr(3),
D => ddr_dq_in(28),
DPRA0 => fifo_71_rd_addr(0),
DPRA1 => fifo_71_rd_addr(1),
DPRA2 => fifo_71_rd_addr(2),
DPRA3 => fifo_71_rd_addr(3),
WCLK => dqs7_delayed_col0_n,
WE => fifo_71_wr_en );
fifo0_bit29 : RAM16X1D
port map (DPO => fifo_70_data_out(1),
A0 => fifo_70_wr_addr(0),
A1 => fifo_70_wr_addr(1),
A2 => fifo_70_wr_addr(2),
A3 => fifo_70_wr_addr(3),
D => ddr_dq_in(29),
DPRA0 => fifo_70_rd_addr(0),
DPRA1 => fifo_70_rd_addr(1),
DPRA2 => fifo_70_rd_addr(2),
DPRA3 => fifo_70_rd_addr(3),
WCLK => dqs7_delayed_col0,
WE => fifo_70_wr_en );
fifo1_bit29 : RAM16X1D
port map (DPO => fifo_71_data_out(1),
A0 => fifo_71_wr_addr(0),
A1 => fifo_71_wr_addr(1),
A2 => fifo_71_wr_addr(2),
A3 => fifo_71_wr_addr(3),
D => ddr_dq_in(29),
DPRA0 => fifo_71_rd_addr(0),
DPRA1 => fifo_71_rd_addr(1),
DPRA2 => fifo_71_rd_addr(2),
DPRA3 => fifo_71_rd_addr(3),
WCLK => dqs7_delayed_col0_n,
WE => fifo_71_wr_en );
fifo0_bit30 : RAM16X1D
port map (DPO => fifo_70_data_out(2),
A0 => fifo_70_wr_addr(0),
A1 => fifo_70_wr_addr(1),
A2 => fifo_70_wr_addr(2),
A3 => fifo_70_wr_addr(3),
D => ddr_dq_in(30),
DPRA0 => fifo_70_rd_addr(0),
DPRA1 => fifo_70_rd_addr(1),
DPRA2 => fifo_70_rd_addr(2),
DPRA3 => fifo_70_rd_addr(3),
WCLK => dqs7_delayed_col0,
WE => fifo_70_wr_en );
fifo1_bit30 : RAM16X1D
port map (DPO => fifo_71_data_out(2),
A0 => fifo_71_wr_addr(0),
A1 => fifo_71_wr_addr(1),
A2 => fifo_71_wr_addr(2),
A3 => fifo_71_wr_addr(3),
D => ddr_dq_in(30),
DPRA0 => fifo_71_rd_addr(0),
DPRA1 => fifo_71_rd_addr(1),
DPRA2 => fifo_71_rd_addr(2),
DPRA3 => fifo_71_rd_addr(3),
WCLK => dqs7_delayed_col0_n,
WE => fifo_71_wr_en );
fifo0_bit31 : RAM16X1D
port map (DPO => fifo_70_data_out(3),
A0 => fifo_70_wr_addr(0),
A1 => fifo_70_wr_addr(1),
A2 => fifo_70_wr_addr(2),
A3 => fifo_70_wr_addr(3),
D => ddr_dq_in(31),
DPRA0 => fifo_70_rd_addr(0),
DPRA1 => fifo_70_rd_addr(1),
DPRA2 => fifo_70_rd_addr(2),
DPRA3 => fifo_70_rd_addr(3),
WCLK => dqs7_delayed_col0,
WE => fifo_70_wr_en );
fifo1_bit31 : RAM16X1D
port map (DPO => fifo_71_data_out(3),
A0 => fifo_71_wr_addr(0),
A1 => fifo_71_wr_addr(1),
A2 => fifo_71_wr_addr(2),
A3 => fifo_71_wr_addr(3),
D => ddr_dq_in(31),
DPRA0 => fifo_71_rd_addr(0),
DPRA1 => fifo_71_rd_addr(1),
DPRA2 => fifo_71_rd_addr(2),
DPRA3 => fifo_71_rd_addr(3),
WCLK => dqs7_delayed_col0_n,
WE => fifo_71_wr_en );
--- Nibble8 instantiation
fifo0_bit32 : RAM16X1D
port map (DPO => fifo_80_data_out(0),
A0 => fifo_80_wr_addr(0),
A1 => fifo_80_wr_addr(1),
A2 => fifo_80_wr_addr(2),
A3 => fifo_80_wr_addr(3),
D => ddr_dq_in(32),
DPRA0 => fifo_80_rd_addr(0),
DPRA1 => fifo_80_rd_addr(1),
DPRA2 => fifo_80_rd_addr(2),
DPRA3 => fifo_80_rd_addr(3),
WCLK => dqs8_delayed_col0,
WE => fifo_80_wr_en );
fifo1_bit32 : RAM16X1D
port map (DPO => fifo_81_data_out(0),
A0 => fifo_81_wr_addr(0),
A1 => fifo_81_wr_addr(1),
A2 => fifo_81_wr_addr(2),
A3 => fifo_81_wr_addr(3),
D => ddr_dq_in(32),
DPRA0 => fifo_81_rd_addr(0),
DPRA1 => fifo_81_rd_addr(1),
DPRA2 => fifo_81_rd_addr(2),
DPRA3 => fifo_81_rd_addr(3),
WCLK => dqs8_delayed_col0_n,
WE => fifo_81_wr_en );
fifo0_bit33 : RAM16X1D
port map (DPO => fifo_80_data_out(1),
A0 => fifo_80_wr_addr(0),
A1 => fifo_80_wr_addr(1),
A2 => fifo_80_wr_addr(2),
A3 => fifo_80_wr_addr(3),
D => ddr_dq_in(33),
DPRA0 => fifo_80_rd_addr(0),
DPRA1 => fifo_80_rd_addr(1),
DPRA2 => fifo_80_rd_addr(2),
DPRA3 => fifo_80_rd_addr(3),
WCLK => dqs8_delayed_col0,
WE => fifo_80_wr_en );
fifo1_bit33 : RAM16X1D
port map (DPO => fifo_81_data_out(1),
A0 => fifo_81_wr_addr(0),
A1 => fifo_81_wr_addr(1),
A2 => fifo_81_wr_addr(2),
A3 => fifo_81_wr_addr(3),
D => ddr_dq_in(33),
DPRA0 => fifo_81_rd_addr(0),
DPRA1 => fifo_81_rd_addr(1),
DPRA2 => fifo_81_rd_addr(2),
DPRA3 => fifo_81_rd_addr(3),
WCLK => dqs8_delayed_col0_n,
WE => fifo_81_wr_en );
fifo0_bit34 : RAM16X1D
port map (DPO => fifo_80_data_out(2),
A0 => fifo_80_wr_addr(0),
A1 => fifo_80_wr_addr(1),
A2 => fifo_80_wr_addr(2),
A3 => fifo_80_wr_addr(3),
D => ddr_dq_in(34),
DPRA0 => fifo_80_rd_addr(0),
DPRA1 => fifo_80_rd_addr(1),
DPRA2 => fifo_80_rd_addr(2),
DPRA3 => fifo_80_rd_addr(3),
WCLK => dqs8_delayed_col0,
WE => fifo_80_wr_en );
fifo1_bit34 : RAM16X1D
port map (DPO => fifo_81_data_out(2),
A0 => fifo_81_wr_addr(0),
A1 => fifo_81_wr_addr(1),
A2 => fifo_81_wr_addr(2),
A3 => fifo_81_wr_addr(3),
D => ddr_dq_in(34),
DPRA0 => fifo_81_rd_addr(0),
DPRA1 => fifo_81_rd_addr(1),
DPRA2 => fifo_81_rd_addr(2),
DPRA3 => fifo_81_rd_addr(3),
WCLK => dqs8_delayed_col0_n,
WE => fifo_81_wr_en );
fifo0_bit35 : RAM16X1D
port map (DPO => fifo_80_data_out(3),
A0 => fifo_80_wr_addr(0),
A1 => fifo_80_wr_addr(1),
A2 => fifo_80_wr_addr(2),
A3 => fifo_80_wr_addr(3),
D => ddr_dq_in(35),
DPRA0 => fifo_80_rd_addr(0),
DPRA1 => fifo_80_rd_addr(1),
DPRA2 => fifo_80_rd_addr(2),
DPRA3 => fifo_80_rd_addr(3),
WCLK => dqs8_delayed_col0,
WE => fifo_80_wr_en );
fifo1_bit35 : RAM16X1D
port map (DPO => fifo_81_data_out(3),
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