📄 data_path_iobs_48bit.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify;
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
use work.parameter_48bit.all;
entity data_path_iobs_48bit is
port(
clk : in std_logic;
clk90 : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
reset90_r : in std_logic;
dqs_reset : in std_logic;
dqs_enable : in std_logic;
ddr_dqs : inout std_logic_vector(11 downto 0);
ddr_dq : inout std_logic_vector(47 downto 0);
write_data_falling: in std_logic_vector(47 downto 0);
write_data_rising : in std_logic_vector(47 downto 0);
write_en_val : in std_logic;
data_mask_f : in std_logic_vector(5 downto 0);
data_mask_r : in std_logic_vector(5 downto 0);
dqs_int_delay_in0 : out std_logic;
dqs_int_delay_in1 : out std_logic;
dqs_int_delay_in2 : out std_logic;
dqs_int_delay_in3 : out std_logic;
dqs_int_delay_in4 : out std_logic;
dqs_int_delay_in5 : out std_logic;
dqs_int_delay_in6 : out std_logic;
dqs_int_delay_in7 : out std_logic;
dqs_int_delay_in8 : out std_logic;
dqs_int_delay_in9: out std_logic;
dqs_int_delay_in10: out std_logic;
dqs_int_delay_in11: out std_logic;
ddr_dq_val : out std_logic_vector(47 downto 0);
ddr_dm : out std_logic_vector(5 downto 0)
);
end data_path_iobs_48bit;
architecture arc_data_path_iobs_48bit of data_path_iobs_48bit is
attribute syn_keep : boolean; -- Using Syn_Keep Derictive
component ddr_dqs_iob
port(
clk : in std_logic;
clk180 : in std_logic;
ddr_dqs_reset : in std_logic;
ddr_dqs_enable : in std_logic;
ddr_dqs : inout std_logic;
dqs : out std_logic
);
end component;
component ddr_dq_iob
port (
ddr_dq_inout : inout std_logic; --Bi-directional SDRAM data bus
write_data_falling : in std_logic; --Transmit data, output on falling edge
write_data_rising : in std_logic; --Transmit data, output on rising edge
read_data_in : out std_logic; -- Received data
clk90 : in std_logic; --Clock 90
clk270 : in std_logic;
write_en_val : in std_logic; --Transmit enable
reset : in std_logic);
end component;
component ddr1_dm_48bit
port (
ddr_dm : out std_logic_vector(5 downto 0);
mask_falling : in std_logic_vector(5 downto 0);
mask_rising : in std_logic_vector(5 downto 0);
clk90 : in std_logic;
clk270 : in std_logic
);
end component;
--SYN_REMOVECOMMENT signal clk270 : std_logic;
--SYN_REMOVECOMMENT signal clk180 : std_logic;
signal ddr_dq_in : std_logic_vector(47 downto 0);
--SYN_REMOVECOMMENT attribute syn_keep of clk180 : signal is true;
--SYN_REMOVECOMMENT attribute syn_keep of clk270 : signal is true;
begin
--SYN_REMOVECOMMENT clk270 <= not clk90;
--SYN_REMOVECOMMENT clk180 <= not clk;
ddr_dq_val <= ddr_dq_in;
ddr1_dm0 : ddr1_dm_48bit port map (
ddr_dm => ddr_dm,
mask_falling => data_mask_f,
mask_rising => data_mask_r,
clk90 => clk90,
clk270 => clk270
);
--***********************************************************************
-- Read Data Capture Module Instantiations
--***********************************************************************
-- DQS IOB instantiations
--***********************************************************************
ddr_dqs_iob0 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(0),
dqs => dqs_int_delay_in0
);
ddr_dqs_iob1 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(1),
dqs => dqs_int_delay_in1
);
ddr_dqs_iob2 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(2),
dqs => dqs_int_delay_in2
);
ddr_dqs_iob3 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(3),
dqs => dqs_int_delay_in3
);
ddr_dqs_iob4 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(4),
dqs => dqs_int_delay_in4
);
ddr_dqs_iob5 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(5),
dqs => dqs_int_delay_in5
);
ddr_dqs_iob6 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(6),
dqs => dqs_int_delay_in6
);
ddr_dqs_iob7 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(7),
dqs => dqs_int_delay_in7
);
ddr_dqs_iob8 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(8),
dqs => dqs_int_delay_in8
);
ddr_dqs_iob9 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(9),
dqs => dqs_int_delay_in9
);
ddr_dqs_iob10 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(10),
dqs => dqs_int_delay_in10
);
ddr_dqs_iob11 : ddr_dqs_iob port map (
clk => clk,
clk180 => clk180,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(11),
dqs => dqs_int_delay_in11
);
--******************************************************************************************************************************
-- DDR Data bit instantiations (56-bits)
--******************************************************************************************************************************
ddr_dq_iob0 : ddr_dq_iob port map(
ddr_dq_inout => ddr_dq(0),
write_data_falling => write_data_falling(0),
write_data_rising => write_data_rising(0),
read_data_in => ddr_dq_in(0),
clk90 => clk90,
clk270 => clk270,
write_en_val => write_en_val,
reset => reset90_r
);
ddr_dq_iob1 : ddr_dq_iob port map(
ddr_dq_inout => ddr_dq(1),
write_data_falling => write_data_falling(1),
write_data_rising => write_data_rising(1),
read_data_in => ddr_dq_in(1),
clk90 => clk90,
clk270 => clk270,
write_en_val => write_en_val,
reset => reset90_r
);
ddr_dq_iob2 : ddr_dq_iob port map(
ddr_dq_inout => ddr_dq(2),
write_data_falling => write_data_falling(2),
write_data_rising => write_data_rising(2),
read_data_in => ddr_dq_in(2),
clk90 => clk90,
clk270 => clk270,
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