data_read_controller_72bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

signal fifo_60_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_61_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_70_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_71_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_80_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_81_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_90_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_91_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_100_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_101_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_110_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_111_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_120_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_121_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_130_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_131_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_140_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_141_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_150_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_151_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_160_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_161_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_170_wr_addr       : std_logic_vector(3 downto 0);
signal fifo_171_wr_addr       : std_logic_vector(3 downto 0);


signal read_valid_data_0_1    : std_logic;
signal read_valid_data_1      : std_logic;

-- SIGNALS ADDED BY MURTHY

signal dqs0_delayed_col0	: std_logic;
signal dqs1_delayed_col0	: std_logic;
signal dqs2_delayed_col0	: std_logic;
signal dqs3_delayed_col0	: std_logic;
signal dqs4_delayed_col0	: std_logic;
signal dqs5_delayed_col0	: std_logic;
signal dqs6_delayed_col0	: std_logic;
signal dqs7_delayed_col0	: std_logic;
signal dqs8_delayed_col0	: std_logic;
signal dqs9_delayed_col0	: std_logic;
signal dqs10_delayed_col0	: std_logic;
signal dqs11_delayed_col0	: std_logic;
signal dqs12_delayed_col0	: std_logic;
signal dqs13_delayed_col0	: std_logic;
signal dqs14_delayed_col0	: std_logic;
signal dqs15_delayed_col0	: std_logic;
signal dqs16_delayed_col0	: std_logic;
signal dqs17_delayed_col0	: std_logic;

signal dqs0_delayed_col1	: std_logic;
signal dqs1_delayed_col1	: std_logic;
signal dqs2_delayed_col1	: std_logic;
signal dqs3_delayed_col1	: std_logic;
signal dqs4_delayed_col1	: std_logic;
signal dqs5_delayed_col1	: std_logic;
signal dqs6_delayed_col1	: std_logic;
signal dqs7_delayed_col1	: std_logic;
signal dqs8_delayed_col1	: std_logic;
signal dqs9_delayed_col1	: std_logic;
signal dqs10_delayed_col1	: std_logic;
signal dqs11_delayed_col1	: std_logic;
signal dqs12_delayed_col1	: std_logic;
signal dqs13_delayed_col1	: std_logic;
signal dqs14_delayed_col1	: std_logic;
signal dqs15_delayed_col1	: std_logic;
signal dqs16_delayed_col1	: std_logic;
signal dqs17_delayed_col1	: std_logic;

---------------------------------------------------------------------------------
-- dqsx_delayed_col0 negated signals
-- used for capturing negedge data into FIFO_*1

signal dqs0_delayed_col0_n	: std_logic;
signal dqs1_delayed_col0_n : std_logic;
signal dqs2_delayed_col0_n	: std_logic;
signal dqs3_delayed_col0_n : std_logic;
signal dqs4_delayed_col0_n	: std_logic;
signal dqs5_delayed_col0_n : std_logic;
signal dqs6_delayed_col0_n	: std_logic;
signal dqs7_delayed_col0_n : std_logic;
signal dqs8_delayed_col0_n	: std_logic;
signal dqs9_delayed_col0_n  : std_logic;
signal dqs10_delayed_col0_n	: std_logic;
signal dqs11_delayed_col0_n	: std_logic;
signal dqs12_delayed_col0_n	: std_logic;
signal dqs13_delayed_col0_n	: std_logic;
signal dqs14_delayed_col0_n	: std_logic;
signal dqs15_delayed_col0_n	: std_logic;
signal dqs16_delayed_col0_n	: std_logic;
signal dqs17_delayed_col0_n	: std_logic;

-- Directive for synthesis   
attribute syn_keep of dqs0_delayed_col0_n : signal is true;
attribute syn_keep of dqs1_delayed_col0_n : signal is true;
attribute syn_keep of dqs2_delayed_col0_n : signal is true;
attribute syn_keep of dqs3_delayed_col0_n : signal is true;
attribute syn_keep of dqs4_delayed_col0_n : signal is true;
attribute syn_keep of dqs5_delayed_col0_n : signal is true;
attribute syn_keep of dqs6_delayed_col0_n : signal is true;
attribute syn_keep of dqs7_delayed_col0_n : signal is true;
attribute syn_keep of dqs8_delayed_col0_n : signal is true;
attribute syn_keep of dqs9_delayed_col0_n : signal is true;
attribute syn_keep of dqs10_delayed_col0_n : signal is true;
attribute syn_keep of dqs11_delayed_col0_n : signal is true;
attribute syn_keep of dqs12_delayed_col0_n : signal is true;
attribute syn_keep of dqs13_delayed_col0_n : signal is true;
attribute syn_keep of dqs14_delayed_col0_n : signal is true;
attribute syn_keep of dqs15_delayed_col0_n : signal is true;
attribute syn_keep of dqs16_delayed_col0_n : signal is true;
attribute syn_keep of dqs17_delayed_col0_n : signal is true;

signal dqs0_delayed_col1_n	: std_logic;
signal dqs1_delayed_col1_n : std_logic;
signal dqs2_delayed_col1_n	: std_logic;
signal dqs3_delayed_col1_n : std_logic;
signal dqs4_delayed_col1_n	: std_logic;
signal dqs5_delayed_col1_n : std_logic;
signal dqs6_delayed_col1_n	: std_logic;
signal dqs7_delayed_col1_n : std_logic;
signal dqs8_delayed_col1_n	: std_logic;
signal dqs9_delayed_col1_n	: std_logic;
signal dqs10_delayed_col1_n	: std_logic;
signal dqs11_delayed_col1_n	: std_logic;
signal dqs12_delayed_col1_n	: std_logic;
signal dqs13_delayed_col1_n	: std_logic;
signal dqs14_delayed_col1_n	: std_logic;
signal dqs15_delayed_col1_n	: std_logic;
signal dqs16_delayed_col1_n	: std_logic;
signal dqs17_delayed_col1_n	: std_logic;

-- Directive for synthesis   
attribute syn_keep of dqs0_delayed_col1_n : signal is true;
attribute syn_keep of dqs1_delayed_col1_n : signal is true;
attribute syn_keep of dqs2_delayed_col1_n : signal is true;
attribute syn_keep of dqs3_delayed_col1_n : signal is true;
attribute syn_keep of dqs4_delayed_col1_n : signal is true;
attribute syn_keep of dqs5_delayed_col1_n : signal is true;
attribute syn_keep of dqs6_delayed_col1_n : signal is true;
attribute syn_keep of dqs7_delayed_col1_n : signal is true;
attribute syn_keep of dqs8_delayed_col1_n : signal is true;
attribute syn_keep of dqs9_delayed_col1_n : signal is true;
attribute syn_keep of dqs10_delayed_col1_n : signal is true;
attribute syn_keep of dqs11_delayed_col1_n : signal is true;
attribute syn_keep of dqs12_delayed_col1_n : signal is true;
attribute syn_keep of dqs13_delayed_col1_n : signal is true;
attribute syn_keep of dqs14_delayed_col1_n : signal is true;
attribute syn_keep of dqs15_delayed_col1_n : signal is true;
attribute syn_keep of dqs16_delayed_col1_n : signal is true;
attribute syn_keep of dqs17_delayed_col1_n : signal is true;


-- FIFO WRITE ENABLE SIGNALS

signal fifo_00_wr_en			:  std_logic;
signal fifo_10_wr_en			:  std_logic;
signal fifo_20_wr_en			:  std_logic;
signal fifo_30_wr_en			:  std_logic;
signal fifo_40_wr_en			:  std_logic;
signal fifo_50_wr_en			:  std_logic;
signal fifo_60_wr_en			:  std_logic;
signal fifo_70_wr_en			:  std_logic;
signal fifo_80_wr_en			:  std_logic;
signal fifo_90_wr_en			:  std_logic;
signal fifo_100_wr_en			:  std_logic;
signal fifo_110_wr_en			:  std_logic;
signal fifo_120_wr_en			:  std_logic;
signal fifo_130_wr_en			:  std_logic;
signal fifo_140_wr_en			:  std_logic;
signal fifo_150_wr_en			:  std_logic;
signal fifo_160_wr_en			:  std_logic;
signal fifo_170_wr_en			:  std_logic;

signal fifo_01_wr_en			:  std_logic;
signal fifo_11_wr_en			:  std_logic;
signal fifo_21_wr_en			:  std_logic;
signal fifo_31_wr_en			:  std_logic;
signal fifo_41_wr_en			:  std_logic;
signal fifo_51_wr_en			:  std_logic;
signal fifo_61_wr_en			:  std_logic;
signal fifo_71_wr_en			:  std_logic;
signal fifo_81_wr_en			:  std_logic;
signal fifo_91_wr_en			:  std_logic;
signal fifo_101_wr_en			:  std_logic;
signal fifo_111_wr_en			:  std_logic;
signal fifo_121_wr_en			:  std_logic;
signal fifo_131_wr_en			:  std_logic;
signal fifo_141_wr_en			:  std_logic;
signal fifo_151_wr_en			:  std_logic;
signal fifo_161_wr_en			:  std_logic;
signal fifo_171_wr_en			:  std_logic;

-- FIFO_WR_POINTER Delayed signals in clk90 domain

signal fifo_00_wr_addr_d        : std_logic_vector(3 downto 0);
signal fifo_00_wr_addr_2d       : std_logic_vector(3 downto 0);

signal fifo_01_wr_addr_d        : std_logic_vector(3 downto 0);
signal fifo_01_wr_addr_2d       : std_logic_vector(3 downto 0);

-- DDR_DQ_IN signals from DDR_DQ Input buffer

signal ddr_dq_in	      :	std_logic_vector(71 downto 0);

signal write_data270_1        : std_logic_vector(71 downto 0);
signal write_data270_2        : std_logic_vector(71 downto 0);
signal rst_dqs_div			      : std_logic;

signal rst_dqs_delay_0_n      : std_logic;
signal rst_dqs_delay_1_n      : std_logic;
signal rst_dqs_delay_2_n      : std_logic;
signal rst_dqs_delay_3_n      : std_logic;
signal rst_dqs_delay_4_n      : std_logic;
signal rst_dqs_delay_5_n      : std_logic;
signal rst_dqs_delay_6_n      : std_logic;
signal rst_dqs_delay_7_n      : std_logic;
signal rst_dqs_delay_8_n      : std_logic;
signal rst_dqs_delay_9_n      : std_logic; 
signal rst_dqs_delay_10_n     : std_logic; 
signal rst_dqs_delay_11_n     : std_logic; 
signal rst_dqs_delay_12_n     : std_logic; 
signal rst_dqs_delay_13_n     : std_logic; 
signal rst_dqs_delay_14_n     : std_logic; 
signal rst_dqs_delay_15_n     : std_logic; 
signal rst_dqs_delay_16_n     : std_logic; 
signal rst_dqs_delay_17_n     : std_logic; 


signal    fifo_00_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_01_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_10_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_11_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_20_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_21_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_30_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_31_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_40_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_41_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_50_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_51_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_60_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_61_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_70_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_71_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_80_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_81_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_90_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_91_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_100_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_101_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_110_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_111_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_120_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_121_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_130_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_131_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_140_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_141_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_150_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_151_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_160_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_161_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_170_rd_addr   : std_logic_vector(3 downto 0);
signal    fifo_171_rd_addr   : std_logic_vector(3 downto 0);

 begin

 fifo_00_wr_addr_val <= fifo_00_wr_addr; 
 fifo_01_wr_addr_val <= fifo_01_wr_addr; 
 fifo_10_wr_addr_val <= fifo_10_wr_addr; 
 fifo_11_wr_addr_val <= fifo_11_wr_addr; 
 fifo_20_wr_addr_val <= fifo_20_wr_addr; 
 fifo_21_wr_addr_val <= fifo_21_wr_addr; 
 fifo_30_wr_addr_val <= fifo_30_wr_addr; 
 fifo_31_wr_addr_val <= fifo_31_wr_addr; 
 fifo_40_wr_addr_val <= fifo_40_wr_addr; 
 fifo_41_wr_addr_val <= fifo_41_wr_addr; 
 fifo_50_wr_addr_val <= fifo_50_wr_addr; 
 fifo_51_wr_addr_val <= fifo_51_wr_addr; 
 fifo_60_wr_addr_val <= fifo_60_wr_addr; 
 fifo_61_wr_addr_val <= fifo_61_wr_addr; 
 fifo_70_wr_addr_val <= fifo_70_wr_addr; 
 fifo_71_wr_addr_val <= fifo_71_wr_addr; 
 fifo_80_wr_addr_val <= fifo_80_wr_addr; 
 fifo_81_wr_addr_val <= fifo_81_wr_addr;
 fifo_90_wr_addr_val <= fifo_90_wr_addr; 
 fifo_91_wr_addr_val <= fifo_91_wr_addr; 
 fifo_100_wr_addr_val <= fifo_100_wr_addr; 
 fifo_101_wr_addr_val <= fifo_101_wr_addr; 
 fifo_110_wr_addr_val <= fifo_110_wr_addr; 
 fifo_111_wr_addr_val <= fifo_111_wr_addr; 
 fifo_120_wr_addr_val <= fifo_120_wr_addr; 
 fifo_121_wr_addr_val <= fifo_121_wr_addr; 
 fifo_130_wr_addr_val <= fifo_130_wr_addr; 
 fifo_131_wr_addr_val <= fifo_131_wr_addr; 
 fifo_140_wr_addr_val <= fifo_140_wr_addr; 
 fifo_141_wr_addr_val <= fifo_141_wr_addr; 
 fifo_150_wr_addr_val <= fifo_150_wr_addr; 
 fifo_151_wr_addr_val <= fifo_151_wr_addr; 
 fifo_160_wr_addr_val <= fifo_160_wr_addr; 
 fifo_161_wr_addr_val <= fifo_161_wr_addr; 
 fifo_170_wr_addr_val <= fifo_170_wr_addr; 
 fifo_171_wr_addr_val <= fifo_171_wr_addr;

 fifo_00_wr_en_val   <=	fifo_00_wr_en;