infrastructure_iobs_72bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

                         R => gnd, 
                         S => gnd); 

U17 : FDDRRSE port map ( 
                        Q => ddr1_clk8_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U18 : FDDRRSE port map ( 
                        Q => ddr1_clk8b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd);

U19 : FDDRRSE port map ( 
                        Q => ddr1_clk9_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U20 : FDDRRSE port map ( 
                        Q => ddr1_clk9b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd);

U21 : FDDRRSE port map ( 
                        Q => ddr1_clk10_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U22 : FDDRRSE port map ( 
                        Q => ddr1_clk10b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd); 
 
U23 : FDDRRSE port map ( 
                        Q => ddr1_clk11_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U24 : FDDRRSE port map ( 
                        Q => ddr1_clk11b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd); 
 
U25 : FDDRRSE port map ( 
                        Q => ddr1_clk12_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U26 : FDDRRSE port map ( 
                        Q => ddr1_clk12b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd); 

U27 : FDDRRSE port map ( 
                        Q => ddr1_clk13_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U28 : FDDRRSE port map ( 
                        Q => ddr1_clk13b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd);

U29 : FDDRRSE port map ( 
                        Q => ddr1_clk14_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U30 : FDDRRSE port map ( 
                        Q => ddr1_clk14b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd);

U31 : FDDRRSE port map ( 
                        Q => ddr1_clk15_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U32 : FDDRRSE port map ( 
                        Q => ddr1_clk15b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd); 
 
U33 : FDDRRSE port map ( 
                        Q => ddr1_clk16_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U34 : FDDRRSE port map ( 
                        Q => ddr1_clk16b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd); 
 
U35 : FDDRRSE port map ( 
                        Q => ddr1_clk17_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => vcc, 
                        D1 => gnd, 
                         R => gnd, 
                         S => gnd); 
 
U36 : FDDRRSE port map ( 
                        Q => ddr1_clk17b_q , 
                        C0 => clk0, 
                        C1 => clk180, 
                        CE => vcc, 
                        D0 => gnd, 
                        D1 => vcc, 
                         R => gnd, 
                         S => gnd); 


---- ******************************************
---- Ouput BUffers for ddr clk's and dimm clk's
---- ******************************************


r1 : OBUF port map (
                     I => ddr1_clk0_q,
                     O => ddr1_clk0);

r2 : OBUF port map (
                     I => ddr1_clk0b_q,
                     O => ddr1_clk0b);

r3 : OBUF port map (
                     I => ddr1_clk1_q,
                     O => ddr1_clk1);

r4 : OBUF port map (
                     I => ddr1_clk1b_q,
                     O => ddr1_clk1b);

r5 : OBUF port map (
                     I => ddr1_clk2_q,
                     O => ddr1_clk2);

r6 : OBUF port map (
                     I => ddr1_clk2b_q,
                     O => ddr1_clk2b);

r7 : OBUF port map (
                     I => ddr1_clk3_q,
                     O => ddr1_clk3);

r8 : OBUF port map (
                     I => ddr1_clk3b_q,
                     O => ddr1_clk3b);

r9 : OBUF port map (
                     I => ddr1_clk4_q,
                     O => ddr1_clk4);

r10 : OBUF port map (
                     I => ddr1_clk4b_q,
                     O => ddr1_clk4b);

r11 : OBUF port map ( 
                     I => ddr1_clk5_q,
                      O => ddr1_clk5); 
  
r12 : OBUF port map ( 
                     I => ddr1_clk5b_q, 
                      O => ddr1_clk5b); 
  
r13 : OBUF port map ( 
                     I => ddr1_clk6_q,
                      O => ddr1_clk6); 
  
r14 : OBUF port map ( 
                     I => ddr1_clk6b_q, 
                      O => ddr1_clk6b); 
  
r15 : OBUF port map ( 
                     I => ddr1_clk7_q,
                      O => ddr1_clk7); 
  
r16 : OBUF port map ( 
                     I => ddr1_clk7b_q, 
                      O => ddr1_clk7b);
r17 : OBUF port map ( 
                     I => ddr1_clk8_q,
                      O => ddr1_clk8); 
  
r18 : OBUF port map ( 
                     I => ddr1_clk8b_q, 
                      O => ddr1_clk8b);

r19 : OBUF port map ( 
                     I => ddr1_clk9_q,
                      O => ddr1_clk9); 
  
r20 : OBUF port map ( 
                     I => ddr1_clk9b_q, 
                      O => ddr1_clk9b);

r21 : OBUF port map ( 
                     I => ddr1_clk10_q,
                      O => ddr1_clk10); 
  
r22 : OBUF port map ( 
                     I => ddr1_clk10b_q, 
                      O => ddr1_clk10b); 
  
r23 : OBUF port map ( 
                     I => ddr1_clk11_q,
                      O => ddr1_clk11); 
  
r24 : OBUF port map ( 
                     I => ddr1_clk11b_q, 
                      O => ddr1_clk11b); 
  
r25 : OBUF port map ( 
                     I => ddr1_clk12_q,
                      O => ddr1_clk12); 
  
r26 : OBUF port map ( 
                     I => ddr1_clk12b_q, 
                      O => ddr1_clk12b);
r27 : OBUF port map ( 
                     I => ddr1_clk13_q,
                      O => ddr1_clk13); 
  
r28 : OBUF port map ( 
                     I => ddr1_clk13b_q, 
                      O => ddr1_clk13b);

r29 : OBUF port map ( 
                     I => ddr1_clk14_q,
                      O => ddr1_clk14); 
  
r30 : OBUF port map ( 
                     I => ddr1_clk14b_q, 
                      O => ddr1_clk14b);

r31 : OBUF port map ( 
                     I => ddr1_clk15_q,
                      O => ddr1_clk15); 
  
r32 : OBUF port map ( 
                     I => ddr1_clk15b_q, 
                      O => ddr1_clk15b); 
  
r33 : OBUF port map ( 
                     I => ddr1_clk16_q,
                      O => ddr1_clk16); 
  
r34 : OBUF port map ( 
                     I => ddr1_clk16b_q, 
                      O => ddr1_clk16b); 
  
r35 : OBUF port map ( 
                     I => ddr1_clk17_q,
                      O => ddr1_clk17); 
  
r36 : OBUF port map ( 
                     I => ddr1_clk17b_q, 
                      O => ddr1_clk17b);

end   arc_infrastructure_iobs_72bit;