📄 data_read_72bit.vhd
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--attribute syn_noprune of dqs8_delayed_col1_n : signal is true;
begin
dqs0_delayed_col0_n <= not dqs0_delayed_col0;
dqs1_delayed_col0_n <= not dqs1_delayed_col0;
dqs2_delayed_col0_n <= not dqs2_delayed_col0;
dqs3_delayed_col0_n <= not dqs3_delayed_col0;
dqs4_delayed_col0_n <= not dqs4_delayed_col0;
dqs5_delayed_col0_n <= not dqs5_delayed_col0;
dqs6_delayed_col0_n <= not dqs6_delayed_col0;
dqs7_delayed_col0_n <= not dqs7_delayed_col0;
dqs8_delayed_col0_n <= not dqs8_delayed_col0;
dqs0_delayed_col1_n <= not dqs0_delayed_col1;
dqs1_delayed_col1_n <= not dqs1_delayed_col1;
dqs2_delayed_col1_n <= not dqs2_delayed_col1;
dqs3_delayed_col1_n <= not dqs3_delayed_col1;
dqs4_delayed_col1_n <= not dqs4_delayed_col1;
dqs5_delayed_col1_n <= not dqs5_delayed_col1;
dqs6_delayed_col1_n <= not dqs6_delayed_col1;
dqs7_delayed_col1_n <= not dqs7_delayed_col1;
dqs8_delayed_col1_n <= not dqs8_delayed_col1;
user_output_data <= first_sdr_data;
fifo0_rd_addr_val <= fifo01_rd_addr;
fifo1_rd_addr_val <= fifo00_rd_addr;
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
fifo_00_data_out_r <= "00000000";
fifo_01_data_out_r <= "00000000";
fifo_10_data_out_r <= "00000000";
fifo_11_data_out_r <= "00000000";
fifo_20_data_out_r <= "00000000";
fifo_21_data_out_r <= "00000000";
fifo_30_data_out_r <= "00000000";
fifo_31_data_out_r <= "00000000";
fifo_40_data_out_r <= "00000000";
fifo_41_data_out_r <= "00000000";
fifo_50_data_out_r <= "00000000";
fifo_51_data_out_r <= "00000000";
fifo_60_data_out_r <= "00000000";
fifo_61_data_out_r <= "00000000";
fifo_70_data_out_r <= "00000000";
fifo_71_data_out_r <= "00000000";
fifo_80_data_out_r <= "00000000";
fifo_81_data_out_r <= "00000000";
else
fifo_00_data_out_r <= fifo_00_data_out;
fifo_01_data_out_r <= fifo_01_data_out;
fifo_10_data_out_r <= fifo_10_data_out;
fifo_11_data_out_r <= fifo_11_data_out;
fifo_20_data_out_r <= fifo_20_data_out;
fifo_21_data_out_r <= fifo_21_data_out;
fifo_30_data_out_r <= fifo_30_data_out;
fifo_31_data_out_r <= fifo_31_data_out;
fifo_40_data_out_r <= fifo_40_data_out;
fifo_41_data_out_r <= fifo_41_data_out;
fifo_50_data_out_r <= fifo_50_data_out;
fifo_51_data_out_r <= fifo_51_data_out;
fifo_60_data_out_r <= fifo_60_data_out;
fifo_61_data_out_r <= fifo_61_data_out;
fifo_70_data_out_r <= fifo_70_data_out;
fifo_71_data_out_r <= fifo_71_data_out;
fifo_80_data_out_r <= fifo_80_data_out;
fifo_81_data_out_r <= fifo_81_data_out;
end if;
end if;
end process;
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
fifo00_rd_addr_r <= "0000";
fifo01_rd_addr_r <= "0000";
fifo10_rd_addr_r <= "0000";
fifo11_rd_addr_r <= "0000";
fifo20_rd_addr_r <= "0000";
fifo21_rd_addr_r <= "0000";
fifo30_rd_addr_r <= "0000";
fifo31_rd_addr_r <= "0000";
fifo40_rd_addr_r <= "0000";
fifo41_rd_addr_r <= "0000";
fifo50_rd_addr_r <= "0000";
fifo51_rd_addr_r <= "0000";
fifo60_rd_addr_r <= "0000";
fifo61_rd_addr_r <= "0000";
fifo70_rd_addr_r <= "0000";
fifo71_rd_addr_r <= "0000";
fifo80_rd_addr_r <= "0000";
fifo81_rd_addr_r <= "0000";
fifop_rd_addr_r <= "0000";
else
fifo00_rd_addr_r <= fifo00_rd_addr;
fifo01_rd_addr_r <= fifo00_rd_addr;
fifo10_rd_addr_r <= fifo00_rd_addr;
fifo11_rd_addr_r <= fifo00_rd_addr;
fifo20_rd_addr_r <= fifo00_rd_addr;
fifo21_rd_addr_r <= fifo00_rd_addr;
fifo30_rd_addr_r <= fifo00_rd_addr;
fifo31_rd_addr_r <= fifo00_rd_addr;
fifo40_rd_addr_r <= fifo00_rd_addr;
fifo41_rd_addr_r <= fifo00_rd_addr;
fifo50_rd_addr_r <= fifo01_rd_addr;
fifo51_rd_addr_r <= fifo01_rd_addr;
fifo60_rd_addr_r <= fifo01_rd_addr;
fifo61_rd_addr_r <= fifo01_rd_addr;
fifo70_rd_addr_r <= fifo01_rd_addr;
fifo71_rd_addr_r <= fifo01_rd_addr;
fifo80_rd_addr_r <= fifo01_rd_addr;
fifo81_rd_addr_r <= fifo01_rd_addr;
fifop_rd_addr_r <= fifo01_rd_addr;
end if;
end if;
end process;
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
first_sdr_data <= (others => '0');
read_valid_data_1_r <= '0';
read_valid_data_1_r1 <= '0';
read_valid_data_1_r2 <= '0';
else
read_valid_data_1_r <= read_valid_data_1;
read_valid_data_1_r1 <= read_valid_data_1_r;
read_valid_data_1_r2 <= read_valid_data_1_r1;
if (read_valid_data_1_r1 = '1') then
first_sdr_data <= ( fifo_80_data_out_r & fifo_70_data_out_r &
fifo_60_data_out_r & fifo_50_data_out_r & fifo_40_data_out_r &
fifo_30_data_out_r & fifo_20_data_out_r & fifo_10_data_out_r &
fifo_00_data_out_r & fifo_81_data_out_r & fifo_71_data_out_r &
fifo_61_data_out_r & fifo_51_data_out_r & fifo_41_data_out_r &
fifo_31_data_out_r & fifo_21_data_out_r & fifo_11_data_out_r &
fifo_01_data_out_r );
else
first_sdr_data <= first_sdr_data;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )
fifo0_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_1,
rgc_gcnt => fifo00_rd_addr
);
fifo1_rd_addr_inst : rd_gray_cntr port map (
clk => clk90,
reset => reset90_r,
cnt_en => read_valid_data_1,
rgc_gcnt => fifo01_rd_addr
);
--*************************************************************************************************************************
-- Dual Port RAM 16x1 instantiations (fifo0 -- Positive edge, fifo1 -- Trailing edge)
--*************************************************************************************************************************
--- Byte0 instantiation
fifo0_bit0 : RAM16X1D
port map (DPO => fifo_00_data_out(0),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(0),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1,
WE => fifo_00_wr_en );
fifo1_bit0 : RAM16X1D
port map (DPO => fifo_01_data_out(0),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(0),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1_n,
WE => fifo_01_wr_en );
fifo0_bit1 : RAM16X1D
port map (DPO => fifo_00_data_out(1),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(1),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit1 : RAM16X1D
port map (DPO => fifo_01_data_out(1),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(1),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
fifo0_bit2 : RAM16X1D
port map (DPO => fifo_00_data_out(2),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(2),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1,
WE => fifo_00_wr_en );
fifo1_bit2 : RAM16X1D
port map (DPO => fifo_01_data_out(2),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(2),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1_n,
WE => fifo_01_wr_en );
fifo0_bit3 : RAM16X1D
port map (DPO => fifo_00_data_out(3),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(3),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit3 : RAM16X1D
port map (DPO => fifo_01_data_out(3),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(3),
DPRA0 => fifo01_rd_addr_r(0),
DPRA1 => fifo01_rd_addr_r(1),
DPRA2 => fifo01_rd_addr_r(2),
DPRA3 => fifo01_rd_addr_r(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
fifo0_bit4 : RAM16X1D
port map (DPO => fifo_00_data_out(4),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(4),
DPRA0 => fifo00_rd_addr_r(0),
DPRA1 => fifo00_rd_addr_r(1),
DPRA2 => fifo00_rd_addr_r(2),
DPRA3 => fifo00_rd_addr_r(3),
WCLK => dqs0_delayed_col1,
WE => fifo_00_wr_en );
fifo1_bit4 : RAM16X1D
port map (DPO => fifo_01_data_out(4),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
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