📄 data_read_72bit.vhd
字号:
D => ddr_dq_in(37),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col0,
WE => fifo_40_wr_en );
fifo1_bit37 : RAM16X1D
port map (DPO => fifo_41_data_out(5),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(37),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
fifo0_bit38 : RAM16X1D
port map (DPO => fifo_40_data_out(6),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(38),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col0,
WE => fifo_40_wr_en );
fifo1_bit38 : RAM16X1D
port map (DPO => fifo_41_data_out(6),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(38),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
fifo0_bit39 : RAM16X1D
port map (DPO => fifo_40_data_out(7),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(39),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col0,
WE => fifo_40_wr_en );
fifo1_bit39 : RAM16X1D
port map (DPO => fifo_41_data_out(7),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(39),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
-- Byte5 Fifo instantiation
fifo0_bit40 : RAM16X1D
port map (DPO => fifo_50_data_out(0),
A0 => fifo_50_wr_addr(0),
A1 => fifo_50_wr_addr(1),
A2 => fifo_50_wr_addr(2),
A3 => fifo_50_wr_addr(3),
D => ddr_dq_in(40),
DPRA0 => fifo_50_rd_addr(0),
DPRA1 => fifo_50_rd_addr(1),
DPRA2 => fifo_50_rd_addr(2),
DPRA3 => fifo_50_rd_addr(3),
WCLK => dqs5_delayed_col0,
WE => fifo_50_wr_en );
fifo1_bit40 : RAM16X1D
port map (DPO => fifo_51_data_out(0),
A0 => fifo_51_wr_addr(0),
A1 => fifo_51_wr_addr(1),
A2 => fifo_51_wr_addr(2),
A3 => fifo_51_wr_addr(3),
D => ddr_dq_in(40),
DPRA0 => fifo_51_rd_addr(0),
DPRA1 => fifo_51_rd_addr(1),
DPRA2 => fifo_51_rd_addr(2),
DPRA3 => fifo_51_rd_addr(3),
WCLK => dqs5_delayed_col0_n,
WE => fifo_51_wr_en );
fifo0_bit41 : RAM16X1D
port map (DPO => fifo_50_data_out(1),
A0 => fifo_50_wr_addr(0),
A1 => fifo_50_wr_addr(1),
A2 => fifo_50_wr_addr(2),
A3 => fifo_50_wr_addr(3),
D => ddr_dq_in(41),
DPRA0 => fifo_50_rd_addr(0),
DPRA1 => fifo_50_rd_addr(1),
DPRA2 => fifo_50_rd_addr(2),
DPRA3 => fifo_50_rd_addr(3),
WCLK => dqs5_delayed_col0,
WE => fifo_50_wr_en );
fifo1_bit41 : RAM16X1D
port map (DPO => fifo_51_data_out(1),
A0 => fifo_51_wr_addr(0),
A1 => fifo_51_wr_addr(1),
A2 => fifo_51_wr_addr(2),
A3 => fifo_51_wr_addr(3),
D => ddr_dq_in(41),
DPRA0 => fifo_51_rd_addr(0),
DPRA1 => fifo_51_rd_addr(1),
DPRA2 => fifo_51_rd_addr(2),
DPRA3 => fifo_51_rd_addr(3),
WCLK => dqs5_delayed_col0_n,
WE => fifo_51_wr_en );
fifo0_bit42 : RAM16X1D
port map (DPO => fifo_50_data_out(2),
A0 => fifo_50_wr_addr(0),
A1 => fifo_50_wr_addr(1),
A2 => fifo_50_wr_addr(2),
A3 => fifo_50_wr_addr(3),
D => ddr_dq_in(42),
DPRA0 => fifo_50_rd_addr(0),
DPRA1 => fifo_50_rd_addr(1),
DPRA2 => fifo_50_rd_addr(2),
DPRA3 => fifo_50_rd_addr(3),
WCLK => dqs5_delayed_col0,
WE => fifo_50_wr_en );
fifo1_bit42 : RAM16X1D
port map (DPO => fifo_51_data_out(2),
A0 => fifo_51_wr_addr(0),
A1 => fifo_51_wr_addr(1),
A2 => fifo_51_wr_addr(2),
A3 => fifo_51_wr_addr(3),
D => ddr_dq_in(42),
DPRA0 => fifo_51_rd_addr(0),
DPRA1 => fifo_51_rd_addr(1),
DPRA2 => fifo_51_rd_addr(2),
DPRA3 => fifo_51_rd_addr(3),
WCLK => dqs5_delayed_col0_n,
WE => fifo_51_wr_en );
fifo0_bit43 : RAM16X1D
port map (DPO => fifo_50_data_out(3),
A0 => fifo_50_wr_addr(0),
A1 => fifo_50_wr_addr(1),
A2 => fifo_50_wr_addr(2),
A3 => fifo_50_wr_addr(3),
D => ddr_dq_in(43),
DPRA0 => fifo_50_rd_addr(0),
DPRA1 => fifo_50_rd_addr(1),
DPRA2 => fifo_50_rd_addr(2),
DPRA3 => fifo_50_rd_addr(3),
WCLK => dqs5_delayed_col0,
WE => fifo_50_wr_en );
fifo1_bit43 : RAM16X1D
port map (DPO => fifo_51_data_out(3),
A0 => fifo_51_wr_addr(0),
A1 => fifo_51_wr_addr(1),
A2 => fifo_51_wr_addr(2),
A3 => fifo_51_wr_addr(3),
D => ddr_dq_in(43),
DPRA0 => fifo_51_rd_addr(0),
DPRA1 => fifo_51_rd_addr(1),
DPRA2 => fifo_51_rd_addr(2),
DPRA3 => fifo_51_rd_addr(3),
WCLK => dqs5_delayed_col0_n,
WE => fifo_51_wr_en );
fifo0_bit44 : RAM16X1D
port map (DPO => fifo_50_data_out(4),
A0 => fifo_50_wr_addr(0),
A1 => fifo_50_wr_addr(1),
A2 => fifo_50_wr_addr(2),
A3 => fifo_50_wr_addr(3),
D => ddr_dq_in(44),
DPRA0 => fifo_50_rd_addr(0),
DPRA1 => fifo_50_rd_addr(1),
DPRA2 => fifo_50_rd_addr(2),
DPRA3 => fifo_50_rd_addr(3),
WCLK => dqs5_delayed_col0,
WE => fifo_50_wr_en );
fifo1_bit44 : RAM16X1D
port map (DPO => fifo_51_data_out(4),
A0 => fifo_51_wr_addr(0),
A1 => fifo_51_wr_addr(1),
A2 => fifo_51_wr_addr(2),
A3 => fifo_51_wr_addr(3),
D => ddr_dq_in(44),
DPRA0 => fifo_51_rd_addr(0),
DPRA1 => fifo_51_rd_addr(1),
DPRA2 => fifo_51_rd_addr(2),
DPRA3 => fifo_51_rd_addr(3),
WCLK => dqs5_delayed_col0_n,
WE => fifo_51_wr_en );
fifo0_bit45 : RAM16X1D
port map (DPO => fifo_50_data_out(5),
A0 => fifo_50_wr_addr(0),
A1 => fifo_50_wr_addr(1),
A2 => fifo_50_wr_addr(2),
A3 => fifo_50_wr_addr(3),
D => ddr_dq_in(45),
DPRA0 => fifo_50_rd_addr(0),
DPRA1 => fifo_50_rd_addr(1),
DPRA2 => fifo_50_rd_addr(2),
DPRA3 => fifo_50_rd_addr(3),
WCLK => dqs5_delayed_col0,
WE => fifo_50_wr_en );
fifo1_bit45 : RAM16X1D
port map (DPO => fifo_51_data_out(5),
A0 => fifo_51_wr_addr(0),
A1 => fifo_51_wr_addr(1),
A2 => fifo_51_wr_addr(2),
A3 => fifo_51_wr_addr(3),
D => ddr_dq_in(45),
DPRA0 => fifo_51_rd_addr(0),
DPRA1 => fifo_51_rd_addr(1),
DPRA2 => fifo_51_rd_addr(2),
DPRA3 => fifo_51_rd_addr(3),
WCLK => dqs5_delayed_col0_n,
WE => fifo_51_wr_en );
fifo0_bit46 : RAM16X1D
port map (DPO => fifo_50_data_out(6),
A0 => fifo_50_wr_addr(0),
A1 => fifo_50_wr_addr(1),
A2 => fifo_50_wr_addr(2),
A3 => fifo_50_wr_addr(3),
D => ddr_dq_in(46),
DPRA0 => fifo_50_rd_addr(0),
DPRA1 => fifo_50_rd_addr(1),
DPRA2 => fifo_50_rd_addr(2),
DPRA3 => fifo_50_rd_addr(3),
WCLK => dqs5_delayed_col0,
WE => fifo_50_wr_en );
fifo1_bit46 : RAM16X1D
port map (DPO => fifo_51_data_out(6),
A0 => fifo_51_wr_addr(0),
A1 => fifo_51_wr_addr(1),
A2 => fifo_51_wr_addr(2),
A3 => fifo_51_wr_addr(3),
D => ddr_dq_in(46),
DPRA0 => fifo_51_rd_addr(0),
DPRA1 => fifo_51_rd_addr(1),
DPRA2 => fifo_51_rd_addr(2),
DPRA3 => fifo_51_rd_addr(3),
WCLK => dqs5_delayed_col0_n,
WE => fifo_51_wr_en );
fifo0_bit47 : RAM16X1D
port map (DPO => fifo_50_data_out(7),
A0 => fifo_50_wr_addr(0),
A1 => fifo_50_wr_addr(1),
A2 => fifo_50_wr_addr(2),
A3 => fifo_50_wr_addr(3),
D => ddr_dq_in(47),
DPRA0 => fifo_50_rd_addr(0),
DPRA1 => fifo_50_rd_addr(1),
DPRA2 => fifo_50_rd_addr(2),
DPRA3 => fifo_50_rd_addr(3),
WCLK => dqs5_delayed_col0,
WE => fifo_50_wr_en );
fifo1_bit47 : RAM16X1D
port map (DPO => fifo_51_data_out(7),
A0 => fifo_51_wr_addr(0),
A1 => fifo_51_wr_addr(1),
A2 => fifo_51_wr_addr(2),
A3 => fifo_51_wr_addr(3),
D => ddr_dq_in(47),
DPRA0 => fifo_51_rd_addr(0),
DPRA1 => fifo_51_rd_addr(1),
DPRA2 => fifo_51_rd_addr(2),
DPRA3 => fifo_51_rd_addr(3),
WCLK => dqs5_delayed_col0_n,
WE => fifo_51_wr_en );
-- Byte6 Fifo instantiation
fifo0_bit48 : RAM16X1D
port map (DPO => fifo_60_data_out(0),
A0 => fifo_60_wr_addr(0),
A1 => fifo_60_wr_addr(1),
A2 => fifo_60_wr_addr(2),
A3 => fifo_60_wr_addr(3),
D => ddr_dq_in(48),
DPRA0 => fifo_60_rd_addr(0),
DPRA1 => fifo_60_rd_addr(1),
DPRA2 => fifo_60_rd_addr(2),
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