data_read_controller_40bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*********************************************************************
-- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins

-- In the current DATA PATH logic DATA CAPTURE part was modified.
-- The below changes were made to reduce the resources in 
-- the data capture

-- in the current architecture data ( dq ) from ddr memory 
-- directly stored into the FIFO's.

-- Architectural changes :

-- Used only TWO FIFOs ( instead of FOUR FIFOs ) 
-- Used Single col ( col0 ) dqs_delayed_col signals
-- Used Gray Counters for write and read pointers of the FIFOs 

-- fbit stage is removed from ddr1_dqbit module ( in the data capture )
-- dq_clk stage was removed 
-- dqs_clk_div logic was removed
-- ddr1_transfer_done logic was removed 
-- data valid signals registering in clk90 domain was removed

-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic  
-- write enable for the FIFOs derived from rst_dqs_div signal


-- Code revised by 	: Narayana Murty.
-- Date 			      : Nov 18, 2003. 

--*********************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--

entity   data_read_controller_40bit  is       
port(
     clk                : in std_logic;
     clk90              : in std_logic;
     reset_r            : in std_logic;
     reset90_r          : in std_logic;
     reset180_r         : in std_logic;
     reset270_r         : in std_logic;
     rst_dqs_div_in     : in std_logic;
     delay_sel          : in std_logic_vector(4 downto 0);   
     dqs_int_delay_in0  : in std_logic;
     dqs_int_delay_in1  : in std_logic;
     dqs_int_delay_in2  : in std_logic;
     dqs_int_delay_in3  : in std_logic;
     dqs_int_delay_in4  : in std_logic;
     dqs_int_delay_in5  : in std_logic;
     dqs_int_delay_in6  : in std_logic;
     dqs_int_delay_in7  : in std_logic;
     dqs_int_delay_in8  : in std_logic; 
     dqs_int_delay_in9  : in std_logic;

    fifo_00_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_01_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_10_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_11_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_20_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_21_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_30_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_31_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_40_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_41_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_50_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_51_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_60_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_61_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_70_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_71_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_80_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_81_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_90_rd_addr_val  : out std_logic_vector(3 downto 0);
    fifo_91_rd_addr_val  : out std_logic_vector(3 downto 0);

     u_data_val   	: out std_logic;
     read_valid_data_1_val : out std_logic;     
     fifo_00_wr_en_val	: out std_logic;	
     fifo_10_wr_en_val	: out std_logic;	
     fifo_20_wr_en_val	: out std_logic;	
     fifo_30_wr_en_val	: out std_logic;
     fifo_40_wr_en_val	: out std_logic;	
     fifo_50_wr_en_val	: out std_logic;	
     fifo_60_wr_en_val	: out std_logic;	
     fifo_70_wr_en_val  : out std_logic;
     fifo_80_wr_en_val	: out std_logic;
     fifo_90_wr_en_val  : out std_logic;
     
     fifo_01_wr_en_val	: out std_logic;	
     fifo_11_wr_en_val	: out std_logic;	
     fifo_21_wr_en_val	: out std_logic;	
     fifo_31_wr_en_val	: out std_logic;
     fifo_41_wr_en_val  : out std_logic;	
     fifo_51_wr_en_val	: out std_logic;	
     fifo_61_wr_en_val	: out std_logic;	
     fifo_71_wr_en_val	: out std_logic;
     fifo_81_wr_en_val	: out std_logic;
     fifo_91_wr_en_val : out std_logic;
     
     fifo_00_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_01_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_10_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_11_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_20_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_21_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_30_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_31_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_40_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_41_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_50_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_51_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_60_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_61_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_70_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_71_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_80_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_81_wr_addr_val : out std_logic_vector(3 downto 0);    
     fifo_90_wr_addr_val : out std_logic_vector(3 downto 0);
     fifo_91_wr_addr_val : out std_logic_vector(3 downto 0);
     
     dqs0_delayed_col1_val  : out std_logic;
     dqs1_delayed_col1_val  : out std_logic;
     dqs2_delayed_col1_val  : out std_logic;
     dqs3_delayed_col1_val  : out std_logic;
     dqs4_delayed_col1_val  : out std_logic;
     dqs5_delayed_col1_val  : out std_logic;
     dqs6_delayed_col1_val  : out std_logic;
     dqs7_delayed_col1_val  : out std_logic;
     dqs8_delayed_col1_val  : out std_logic;
     dqs9_delayed_col1_val  : out std_logic;
     
     dqs0_delayed_col0_n_val: out std_logic;
     dqs1_delayed_col0_n_val: out std_logic;
     dqs2_delayed_col0_n_val: out std_logic;
     dqs3_delayed_col0_n_val: out std_logic;
     dqs4_delayed_col0_n_val: out std_logic;
     dqs5_delayed_col0_n_val: out std_logic;
     dqs6_delayed_col0_n_val: out std_logic;
     dqs7_delayed_col0_n_val: out std_logic;
     dqs8_delayed_col0_n_val: out std_logic;
     dqs9_delayed_col0_n_val: out std_logic
     
      );

end   data_read_controller_40bit;  

architecture   arc_data_read_controller_40bit of   data_read_controller_40bit    is

attribute syn_keep : boolean;  -- Using Syn_Keep Derictive

component dqs_delay                                             
              port (
		    clk_in   : in std_logic;
		    sel_in   : in std_logic_vector(4 downto 0);
		    clk_out  : out std_logic
		  );                                           
end component;

-- wr_gray_cntr is a gray counter with an ASYNC reset for fifo wr_addr
component wr_gray_cntr
	port (
			clk 				: 	in std_logic;         
			reset				:	in std_logic;
			cnt_en			        :	in std_logic;         
			wgc_gcnt			:	out std_logic_vector(3 downto 0)
		  );
end component; 
  
-- fifo_wr_en module generates fifo write enable signal
-- enable is derived from rst_dqs_div signal

-- rd_gray_cntr is a gray counter with a SYNC reset ( reset_90r) for fifo rd_addr
component rd_gray_cntr port (
			clk 				: 	in std_logic;         
			reset				:	in std_logic;
			cnt_en			        :	in std_logic;         
			rgc_gcnt			:	out std_logic_vector(3 downto 0)
		  );
end component; 

component fifo_0_wr_en 
	port
 	(
		clk		: 	in std_logic; 
     		reset		:	in std_logic; 
		din		:	in std_logic;
		rst_dqs_delay_n : 	out std_logic;
		dout		:	out std_logic
	  );
end component;


component fifo_1_wr_en 
	port (
		clk 		:  	in std_logic;
		rst_dqs_delay_n : 	in std_logic;
 	   	reset		:	in std_logic; 
		din		:	in std_logic;
		dout		:	out std_logic
	  );
end component ;


signal dqs_delayed_col0       : std_logic_vector(9 downto 0); 
signal dqs_delayed_col1       : std_logic_vector(9 downto 0); 

signal fifo_00_empty          : std_logic;
signal fifo_01_empty          : std_logic;

signal fifo_00_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_01_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_10_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_11_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_20_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_21_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_30_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_31_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_40_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_41_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_50_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_51_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_60_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_61_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_70_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_71_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_80_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_81_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_90_wr_addr        : std_logic_vector(3 downto 0);
signal fifo_91_wr_addr        : std_logic_vector(3 downto 0);

signal read_valid_data_0_1    : std_logic;
signal read_valid_data_1      : std_logic;

-- SIGNALS ADDED BY MURTHY

signal dqs0_delayed_col0	: std_logic;
signal dqs1_delayed_col0	: std_logic;
signal dqs2_delayed_col0	: std_logic;
signal dqs3_delayed_col0	: std_logic;
signal dqs4_delayed_col0	: std_logic;
signal dqs5_delayed_col0	: std_logic;
signal dqs6_delayed_col0	: std_logic;
signal dqs7_delayed_col0	: std_logic;
signal dqs8_delayed_col0	: std_logic;
signal dqs9_delayed_col0	: std_logic;

signal dqs0_delayed_col1	: std_logic;
signal dqs1_delayed_col1	: std_logic;
signal dqs2_delayed_col1	: std_logic;
signal dqs3_delayed_col1	: std_logic;
signal dqs4_delayed_col1	: std_logic;
signal dqs5_delayed_col1	: std_logic;
signal dqs6_delayed_col1	: std_logic;
signal dqs7_delayed_col1	: std_logic;
signal dqs8_delayed_col1	: std_logic;
signal dqs9_delayed_col1	: std_logic;

---------------------------------------------------------------------------------
-- dqsx_delayed_col0 negated signals
-- used for capturing negedge data into FIFO_*1

signal dqs0_delayed_col0_n	: std_logic;
signal dqs1_delayed_col0_n : std_logic;
signal dqs2_delayed_col0_n	: std_logic;
signal dqs3_delayed_col0_n : std_logic;
signal dqs4_delayed_col0_n	: std_logic;
signal dqs5_delayed_col0_n : std_logic;
signal dqs6_delayed_col0_n	: std_logic;
signal dqs7_delayed_col0_n : std_logic;
signal dqs8_delayed_col0_n	: std_logic;
signal dqs9_delayed_col0_n  : std_logic;

-- Directive for synthesis   
attribute syn_keep of dqs0_delayed_col0_n : signal is true;
attribute syn_keep of dqs1_delayed_col0_n : signal is true;
attribute syn_keep of dqs2_delayed_col0_n : signal is true;
attribute syn_keep of dqs3_delayed_col0_n : signal is true;
attribute syn_keep of dqs4_delayed_col0_n : signal is true;
attribute syn_keep of dqs5_delayed_col0_n : signal is true;
attribute syn_keep of dqs6_delayed_col0_n : signal is true;
attribute syn_keep of dqs7_delayed_col0_n : signal is true;
attribute syn_keep of dqs8_delayed_col0_n : signal is true;
attribute syn_keep of dqs9_delayed_col0_n : signal is true;


signal dqs0_delayed_col1_n	: std_logic;
signal dqs1_delayed_col1_n : std_logic;
signal dqs2_delayed_col1_n	: std_logic;
signal dqs3_delayed_col1_n : std_logic;
signal dqs4_delayed_col1_n	: std_logic;
signal dqs5_delayed_col1_n : std_logic;
signal dqs6_delayed_col1_n	: std_logic;
signal dqs7_delayed_col1_n : std_logic;
signal dqs8_delayed_col1_n	: std_logic;
signal dqs9_delayed_col1_n	: std_logic;